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AR# 30035

9.2i SP4 Virtex-5 - OBUFTDS Slave IOB has incorrect connectivity on tristate enable

Description

When I upgraded to ISE version 9.2i SP4, my design began to fail Bitgen DRC with the message:

"ERROR:PhysDesignRules:368 - The signal <ddr2_dqs_n<3>> is incomplete. The signal

is not driven by any source pin in the design."

When I examine the problem area in FPGA Editor, I see that the connectivity of the tristate enable signal has been corrupted for the slave side of an OBUFTDS.

Solution

This problem will be fixed in ISE version 10.1 SP1. Meanwhile, a patch is available for 9.2i SP4:

Windows 32-bit

http://www.xilinx.com/txpatches/pub/swhelp/ise9_updates/92isp4_map_win_30035.zip
To install, unzip 92isp4_map_win_30035.zip in the Xilinx install directory

while maintaining directory structure.

Windows 64-bit

http://www.xilinx.com/txpatches/pub/swhelp/ise9_updates/92isp4_map_win64_30035.zip
To install, unzip 92isp4_map_win64_30035.zip in the Xilinx install directory

while maintaining directory structure.

Linux 32-bit

http://www.xilinx.com/txpatches/pub/swhelp/ise9_updates/92isp4_map_lin_30035.tar.gz
To install:

cd $Xilinx

tar zxvf 92isp4_map_lin_30035.tar.gz

Linux 64-bit

http://www.xilinx.com/txpatches/pub/swhelp/ise9_updates/92isp4_map_lin64_30035.tar.gz
To install:

cd $Xilinx

tar zxvf 92isp4_map_lin64_30035.tar.gz

AR# 30035
Date Created 01/17/2008
Last Updated 12/15/2012
Status Active
Type General Article