| AR# | 30046 |
| Part | SW-Timing Analyzer/TRCE |
| Last Modified | 2009-07-01 00:00:00.0 |
| Status | Active |
| Keywords | Timing Analyzer, Technology |
Keywords: Timing Analyzer, Technology
When I cross-probe the path listed under the PERIOD constraint to both the physical/implemented technology view and the logical/translated view, the physical/implemented view looks correct and complete, but the logical/translated view is incomplete, only showing the final block in the path.