This Release Notes is for the Block Memory Generator Core v2.7 released in ISE 10.1. It contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
The Xilinx Block Memory Generator v2.7 LogiCORE should be used in all new Virtex-5, Virtex-4, Virtex-II, Virtex-II Pro, Spartan-II/E and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever a block memory is required. This core supersedes the Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on Xilinx.com to convert Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.
Please see the Block Memory Core Migration Kit available at:
A new CORE Generator feature is available to upgrade the Block Memory Generator from v2.4 to the latest core. This feature is part of the CORE Generator, and it is visible only if you open an existing CORE Generator project with a previously generated Block Memory Generator v2.4 core. See the "Upgrading a Core" section of the CORE Generator User Guide (Software Manuals).
(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in the Block Memory Generator
(Xilinx Answer 31378) BitGen DRC Warnings Are Produced When DOA is Unused and DIA is Tied to Ground
New Features in v2.7
- ISE 10.1 software support.
- Improved behavioral simulation time over the v2.6 core.
Resolved Issues in v2.7
- Generating Block Memory Generator takes a long time. - CR 444402
(Xilinx Answer 24313) When using the core for Virtex-4 and Virtex-5 with Byte-write Enable and Write-First Operating Mode, the following warning might be displayed during simulation:
"# ** Warning: Functional warning at simulation time ( 1572 ns)
: RAMB16( :top:bm_tb:test1_dut:bmg0:bmg0:bu2_u0_blk_mem_generator_
port A is in WRITE_FIRST mode requiring all bits of WEA to be all
'1's or all '0's to guarantee valid outputs.
# Time: 1572 ns Iteration: 3 Instance:
- Block Memory Generator GUI incorrectly allows you to select any of the three write modes in the Simple Dual-Port RAM: Simple Dual-Port RAM must allow the Read First mode only. - CR 436053
- Block Memory Generator GUI does not have validation checks for Enable_B and Use_Ramb16bwer_Reset_Behavior, causing failure in generation of ASY symbol and Core netlist respectively. - CR 439672, CR 433594
Known Issues in v2.7
(Xilinx Answer 32037) CORE Generator GUI displays the incorrect latency for an ECC enabled core
(Xilinx Answer 24034) Core does not generate for large memories
The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6 GHz with two Gigabytes of RAM can generate a memory core that is 1.8 MBits or 230 kilobytes. - CR 415768
(Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus
(Xilinx Answer 30401) Block Memory Generator GUI crashes when certain ranges of Write Depth and Write Width values are
selected - CR 433002
The Virtex-4 and Virtex-5 Errata are located at:
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.
Block Memory Generator v2.6 Known Issues
-The Block Memory Generator v2.6 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.6 issues, see (Xilinx Answer 29247).
Block Memory Generator v2.5 Known Issues
-The Block Memory Generator v2.5 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.5 issues, see (Xilinx Answer 25459).
Block Memory Generator v2.4 Known Issues
-The Block Memory Generator v2.4 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.4 issues, see (Xilinx Answer 24555).
Block Memory Generator v2.3 Known Issues
-The Block Memory Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.3 issues, see (Xilinx Answer 24229).
Block Memory Generator v2.2 Known Issues
-The Block Memory Generator v2.2 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.2 issues, see (Xilinx Answer 23849).
06/18/2008 - Initial Release
01/14/2009 - Added AR 32037 to known issues