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AR# 30056

LogiCORE FIFO Generator v4.3 - Release Notes and Known Issues for 10.1 IP Update 0 (10.1_IP0)

Description

Keywords: CORE Generator, IP, update, 10.1i, IP0_K, FIFO, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Note and Known Issues Answer Record is for the FIFO Generator v4.3 Core released in 10.1. It contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Issues

For general CORE Generator known issues and design tools requirements, see (Xilinx Answer 29767).

Solution

General Information
(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a data sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How do I test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator?
(Xilinx Answer 30029) Setup/Hold time violations occur in the Unconstrained Path Report
(Xilinx Answer 31144) Differences between FIFO v4.x cores and v3.x (and prior) cores

New Features in v4.3
- Option to enable or disable the embedded register for Virtex-5 built-in common clock FIFO
- ISE 10.1 support

Bug Fixes in v4.3
(Xilinx Answer 29514) In the Verilog behavioral model, WR_DATA_COUNT behavior in asymmetric FWFT configurations is undefined - CR 449605
(Xilinx Answer 29581) In the Verilog behavioral model, the behavior of programmable full is incorrectly defined for common Clock Shift RAM - CR 450727
(Xilinx Answer 29513) In the VHDL behavioral model, the behavior of underflow flag during reset is undefined - CR 449899
- In the VHDL behavioral model, DOUT is reset even when use_dout_reset is false. The work-around for pre-v4.3 cores is to use the Verilog or Structural model - CR 454156
- In the GUI, Single Programmable Empty assert and Multiple Programmable Empty assert and negate max values are incorrect. The work-around for pre-v4.3 cores is for the user to limit the "Single Prog Empty" to a maximum of (Read Depth - 1), the "Multiple Prog Empty" Assert to a max of (Read Depth - 2), and the "Multiple Prog Empty" Negate to a max of (Read Depth - 1). - CR 448828

Known Issues in v4.3
(Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5
(Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
(Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur
(Xilinx Answer 20271) Simulation error occurs on RESET
(Xilinx Answer 30221) Customization GUI incorrectly advertises FWFT support for certain configurations
(Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected
(Xilinx Answer 30571) Synchronous reset (SRST) does not affect DOUT or EMPTY
(Xilinx Answer 31379) When importing an XCO file user cannot change read/write clock frequencies with Built-in FIFO
(Xilinx Answer 31380) The first word does not fall through in structural simulation of a Common Clock BRAM with FWFT
(Xilinx Answer 31381) Empty flag does not assert in Common Clock (BRAM based) behavioral model simulation
- The "Option to disable timing violations on cross clock domain registers" mentioned in the "readme" and "Version Information" files generated with the core has been pulled from the FIFO v4.3 release.


FIFO Generator v4.2 Known Issues
-The FIFO Generator v4.2 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v4.2 issues, see (Xilinx Answer 29246).

FIFO Generator v4.1 Known Issues
-The FIFO Generator v4.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v4.1 issues, see (Xilinx Answer 25458).

FIFO Generator v3.3 Known Issues
-The FIFO Generator v3.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.3 issues, see (Xilinx Answer 24552).

FIFO Generator v3.2 Known Issues
-The FIFO Generator v3.2 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.2 issues, see (Xilinx Answer 23847).

FIFO Generator v3.1 Known Issues
-The FIFO Generator v3.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 23490).

FIFO Generator v2.3 Known Issues
-The FIFO Generator v2.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 22302).
AR# 30056
Date Created 03/05/2008
Last Updated 08/25/2008
Status Active
Type General Article