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AR# 30057

LogiCORE Distributed Memory Generator v3.4 - Release Notes and Known Issues for 10.1 IP Update 0 (10.1_IP0)


This Release Note is for the Distributed Memory Generator Core v3.4 released in ISE 10.1, and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues


General Information

The Xilinx Distributed Memory Generator v3.4 LogiCORE should be used in all new designs for supported families wherever a distributed memory is required. This core supersedes all versions of the previously released Distributed Memory LogiCORE.

New Features

- ISE 10.1 software support

Bugs Fixed in v3.4

(Xilinx Answer 25360) - DPRA Reg is clocked by CLK unless output registers are used. DPRA Reg should be clocked by QDPO_CLK regardless of whether output registers are implemented - CR 440076

(Xilinx Answer 25361) - Figure 6 of the Distributed RAM data sheet (DS322) shows incorrect clocking for QDPO_CE and QSPO_CE - CR 440140

Known Issues in v3.4

(Xilinx Answer 21393) - When a large Distributed Memory Generator IP is generated, CORE Generator runs out of memory and fails to generate - CR 431917

AR# 30057
Date Created 03/05/2008
Last Updated 12/15/2012
Status Active
Type General Article