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AR# 30059

LogiCORE RapidIO v4.3 - Release Notes and Known Issues for 10.1 IP Update 0 (10.1_IP0)

Description

This Release Note and Known Issues Answer Record is for the RapidIO v4.3 released in 10.1 IP Update 0 and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

General Information

- Starting with v4.1 of the LogiCORE Serial RapidIO solution, the sRIO PHY, RIO Logical IO, and RIO Design Environment Cores have been integrated into a single end-point solution.

- When generating SRIO v4.3 Core, you might see the following message in the CORE Generator console: "Delivering source files for srio_v4_3." Although the example design and buffer module are delivered in the Verilog source files, SRIO PHY and Logical layer modules are delivered in ngc netlist only.

New Features in v4.3

- Support added for ISE 10.1

- Virtex-5 FXT (GTX) support

- SecureIP support

Bug Fixed in v4.3

Core does not have functionality to enable the user to drop unintended packets based on Device ID.

- Version fixed: v4.3.

- CR#455552 - Added a new port called deviceid which indicates the current Device ID value stored in the Base Device ID CSR.

Known Issues in v4.3

(Xilinx Answer 30023) x4 core can train down to x1 using lane 0, but not to other lanes

(Xilinx Answer 30314) Virtex-4, x4 core might intermittently train down to x1 due to MGT lock signal issue **

(Xilinx Answer 30320) Messaging packet has incorrect treq_byte_count **

(Xilinx Answer 30054) CAR value incorrect **

(Xilinx Answer 29936) Maintenance RESPONSE packet has incorrect source device ID **

(Xilinx Answer 30322) Missing EOF or missing packet on target request interface when sending 8-byte SWRITE **

(Xilinx Answer 30323) Re-initialization is not forced following a change to Port Width Override **

(Xilinx Answer 30872) In VHDL design files, port mismatch occurs when synthesizing

(Xilinx Answer 29522) Issues running Synplicity flow

(Xilinx Answer 24967) Select "Engineering Sample" when Targeting ML523 boards Rev A, B or C

(Xilinx Answer 24968) Logical Layer Receive side does not support stalls on incoming Rx packets; the Rx buffer must provide packets to the logical layer without buffer-induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule.

(Xilinx Answer 24970) A control symbol which has been scheduled into the transmit pipeline might be lost if reinitialization is forced.

NOTE: ** denotes: Issues fixed in v4.4 Core scheduled to be released in end June 2008. Please open a Xilinx Technical WebCase if you need the fix for these issues immediately:

http://www.xilinx.com/support/clearexpress/websupport.htm

Known Issues in v4.2

Serial Rapid IO v4.2 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid IO v4.2, see (Xilinx Answer 25462).

Known Issues in v4.1

Serial Rapid IO v4.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid IO v4.1, see (Xilinx Answer 23850).

Known Issues in v3.1

Serial Rapid IO v3.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid IO v3.1, see (Xilinx Answer 22319).

AR# 30059
Date Created 03/10/2008
Last Updated 12/15/2012
Status Active
Type General Article