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AR# 30060

LogiCORE CPRI v1.2 - Release Notes and Known Issues for 10.1 IP Update 0 (10.1_IP0)

Description

This Release Note is for the Common Packet Radio Interface (CPRI) v1.2 released in 10.1 IP Update 1, and contains the following information:

- New Features

- Bug Fixes

- General Information

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

Solution

New Features

- ISE 10.1 software support

- Slave Timing Enable management configuration bit added

Bug Fixes in v1.2

- CR 447048: TX PLL reprogramming causes problems for simprims simulation

- CR 449569: Ethernet FIFO - Very short frames get lodged in receive FIFO

- CR 449561: Change rx_sync_count circuit to reset DCM instead of restarting phase alignment

- CR 449543: CMT PLL Lock signal is not valid for 100 us after reset

- CR 448949: Can no longer use PLL_TXDIVSEL_OUT - use PLL_TXDIVSEL_COMM_OUT

- CR 448948: Lengthen tx_sync procedure

- CR 446096: Slave needs to hold off transmitting until external PLL is locked and stable

- CR 449704: Add synchronizer modules to gtp_and_clocks, tx_clk_gen and rx_clk_gen

- CR 450618: Reorganized and simplified synchronization of clock status signals

- CR 451118: Watchdog timer reset synchronous to wrong clock

- CR 449225: wr_fifo_go is used on wrong clock domain in cdc_fifo.vhd

- CR 449570: Clock domain crossing issues in Ethernet block in packets_empty and fifo_empty signals

- CR 456457: Prevent shift register inference on clock crossing registers in tx_modules, rx_modules, tx_ctrl, tx_eth_cpri

- CR 456466: Added ASYNC_REG attributes to clock crossing registers in tx_modules, rx_modules, tx_ctrl, tx_eth_cpri

- CR 456614: False path causing hold time issue

Known Issues in v1.2

- CR 467345: When an RAI-causing event (Loss of Signal or Loss of Framing) occurs, the core stops transmitting immediately. (Xilinx Answer 30548).

- CR 454889: Setting C_R21_TIMER to false does not omit the FIFO transit time measurement circuit. This does not affect the functionality of the core, but will result in slight increase in resource utilization (41 slices, 71 Reg, 64 LUTS, 28 LUTRAMs).

-(Xilinx Answer 32516) LogiCORE CPRI v1.2 - Default slave CDC FIFO depth too small

Known Issues in v1.1

CPRI v1.1 is now obsolete. Please upgrade to v1.2.

For known issues on CPRI v1.1. Please see (Xilinx Answer 29162)

AR# 30060
Date Created 03/13/2008
Last Updated 12/15/2012
Status Archive
Type General Article