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AR# 30107

Endpoint Block Plus Wrapper for PCI Express - What output should be expected when running the PIO example simulation?


When running the PIO example user design that is provided with the Block Plus Core, what output should be expected?


Make sure you have properly compiled the Xilinx libraries including the SmartModel libraries. When running the simulation, you should see the following output:

***** Registering Synopsys SWIFT PLI tasks *****

Runtime, LMTV v12.33
Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED
Platform Type: linux (32-bit).
You can use the Browser tool to configure the SmartModel
Library and access information about SmartModels:

SmartModel product documentation is available here:

If you do not see the above output, it means the SmartModels are not compiled properly or the simulator is not processing them. If you do see the above output, the simulation starts to run and generates the following output

Running test {smoke_test_0}......
[ 0] : System Reset Asserted...
[ 4995000] : System Reset De-asserted...
[ 8522100] : Transaction Reset Is De-asserted...
[ 88978100] : Transaction Link Is Up...
[ 88978100] : Expected Device/Vendor ID = 000710ee
[ 88978100] : Reading from PCI/PCI-Express Configuration Register 0x00
[ 89002000] : TSK_PARSE_FRAME on Transmit
[ 90650000] : TSK_PARSE_FRAME on Receive
[ 91402000] : TEST PASSED --- Device/Vendor ID 000710ee successfully received

If the core does not seem to be linking up around 88 microseconds as shown above, see (Xilinx Answer 29294).
AR# 30107
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 Integrated Endpoint Block
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