| AR# |
30113 |
| Part |
IP-MPMC |
| Last Modified |
2008-05-14 00:00:00.0 |
| Status |
Active |
| Keywords |
revup, script, mig, ddr2, dqsn, ecc, MPMC_Clk0_DIV2 |
Description
Keywords: revup, script, mig, ddr2, dqsn, ecc, MPMC_Clk0_DIV2
What are the differences between MPMC v3 and MPMC v4?
Solution
Below is a short list of changes that MPMC v3 users should be aware of when migrating to MPMC v4.
1. New MIG v2.1 Virtex-5 DDR2 PHY:
......Migrating MPMC v3 users must run rev up script,
revup_v5_ucf.pl..........New UCF with location constraints and timing constraints
..........New MHS params called C_MEM_DQS_IO_COL and C_MEM_DQ_IO_MS, generated from revup script, or MIG ddr2_sdram.v.
...New clock input called "MPMC_Clk0_DIV2" must be connected with "MPMC_Clk0" signal, synchronously divided by 2.
2. Spartan-3 Generation MIG PHY
......Migrating MPMC v3 users must run rev up script,
revup_s3_ucf.pl3. Changed default value of C_DDR2_DQSN_ENABLE parameter to 1.
4. ECC bits are always a full byte lane wide (8-bits), and all bits must be functional and connected to memory.
