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AR# 30113

10.1 EDK, MPMC v4.00.a - What are the changes between MPMC v3 and MPMC v4?


What are the differences between MPMC v3 and MPMC v4?


Below is a short list of changes that MPMC v3 users should be aware of when migrating to MPMC v4.

1. New MIG v2.1 Virtex-5 DDR2 PHY:

......Migrating MPMC v3 users must run rev up script, revup_v5_ucf.pl

..........New UCF with location constraints and timing constraints

..........New MHS params called C_MEM_DQS_IO_COL and C_MEM_DQ_IO_MS, generated from revup script, or MIG ddr2_sdram.v.

...New clock input called "MPMC_Clk0_DIV2" must be connected with "MPMC_Clk0" signal, synchronously divided by 2.

2. Spartan-3 Generation MIG PHY

......Migrating MPMC v3 users must run rev up script, revup_s3_ucf.pl

3. Changed default value of C_DDR2_DQSN_ENABLE parameter to 1.

4. ECC bits are always a full byte lane wide (8-bits), and all bits must be functional and connected to memory.

AR# 30113
Date Created 02/22/2008
Last Updated 12/15/2012
Status Active
Type General Article