We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30118

LogiCORE Initiator/Target for PCI-X v5.165 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)


This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target for PCI-X v5.165 released in ISE 10.1 Initial IP Update and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf


General Information

The LogiCORE PCI v5.165 supports Virtex-4, Virtex-II Pro, and Virtex-E architectures only. For Virtex-5 devices, use the v6.6 PCI-X Core. For more information on this core, refer to (Xilinx Answer 30119).

- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.

New Features

-ISE 10.1 design suite support

-Example design scripts automatically generated with the user's choice of device

Resolved Issues

-CR447306: Unusually low Latency Timer setting might cause faulty IRDY# disconnect sequence in PCI-X mode

When initiating a transaction, the Initiator/Target for PCI-X would incorrectly deassert IRDY# after the first ADB (but leave FRAME# asserted) if ever ALL the following conditions are met:

- The transaction starts three or fewer data phases before the next ADB

- GNT# is deasserted between the first assertion of FRAME# and the first assertion of TRDY#

- The latency count expires before the first assertion of TRDY#

The Initiator logic has been modified to correct this issue in all Virtex, Virtex-E, and Virtex-4 implementations. It has also been

corrected in Virtex-II and Virtex-II Pro implementations that use PCI-X 66 MHz mode.

Known Issues

-The documentation (User Guide, Getting Started Guide, and Data Sheet) contained in the doc does not contain the most recent versions. The versions delivered with the core are from the 9.2i IP Update 2 release. The most recent documentation can be obtained on the Xilinx Web site. Please follow these steps:

1. Go to: http://www.xilinx.com/support/documentation/index.htm
2. Select the IP Cores.

3. Select Bus Interface and IO.

4. Select PCI/PCI-X core in use.

AR# 30118
Date Created 03/13/2008
Last Updated 12/15/2012
Status Active
Type General Article