We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30134

10.1 EDK, MPMC v4.00.a - How do I revup a design with multiple MPMCv3 MIG cores to MPMCv4?


Keywords: duplicate, DDR, DDR2, upgrade

How do I revup a design with multiple MPMC v3 cores to MPMC v4 cores when using the default MIG-based PHY?


For versions other than Virtex-5 DDR2 MIG PHYs, follow any revup directions from the MPMC data sheet. Most PHY/device combinations do not need any special handling for multiple MPMC designs.

For Virtex-5 DDR2 MIG designs, MIG 2.1 constraints must be added for each MPMC instance. To accomplish this, the "revup_v5_ucf.pl" script must be run twice. For each MPMC instance, execute the script and change the DQ and DQS base names to match the DQ and DQS signal names used for that MPMC from the UCF. Use the output file of each execution as the input to the next. Then continue to follow the revup directions, adding each revup MHS snippet of the C_MEM_DQS_IO_COL and C_MEM_DQ_IO_MS parameters to the corresponding MPMC instance in the MPMC GUIs or system MHS file.

It is recommended that MPMC v4.00.a users use the updated revup scripts found in (Xilinx Answer 29261).
AR# 30134
Date 03/05/2008
Status Active
Type General Article
Page Bookmarked