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AR# 30144

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)


This Answer Record contains the Release Notes for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 Core, which was released in the ISE 10.1 Initial IP Update. It includes the following:  


- New Features  

- Bug Fixes  

- Known Issues 



For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf.


New Features 


- ISE 10.1i software support 

- Virtex-5 FXT support 

- VCS simulator support for Verilog (Linux only) 

- Updated Virtex-5 GTP parameters: PMA_RX_CFG values changed to exclude second-order loop filter 

- Updated Virtex-4 GT11 reset/initialization state machines to match the latest recommendations 


Bug Fixes 


- Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify. This issue does not affect XST. For more information, see (Xilinx Answer 25469)


- ISE Project Navigator GUI : Core Generation Failure 

- CR 453910: the core would fail to generate when using the SGMII standard with the TBI from within the ISE Project Navigator GUI. The core would successfully generate when CORE Generator was run as a standalone tool. This has now been resolved. 


Known Issues 


1. Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down to meet timing. These registers are not included in version v9.1 of the core. If LXT/SXT ES silicon is being used, the RocketIO wrapper files can be regenerated with the GTP wizard. See The RocketIO Transceiver Logic section of UG155 generated with the core for more information. 


2. Virtex-5 Functional or Timing Simulation. In (UniSim) functional simulation or (SimPrim) timing simulation, if TXPOWERDOWN#_IN is "X," this causes GTP outputs TXN/TXP to always be "X." If TXPOWERDOWN#_IN never goes to "X," the problem is not seen. For more information, see (Xilinx Answer 24677)


3. In 10.1 SimPrims the output of X_IDELAY is 'X' in VCS Verilog Simulation. For more information, see (Xilinx Answer 30646)


4. In 10.1 SimPrim Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815)


5. Virtex-5 GTX VCS Verilog functional and timing simulation errors out and does not complete. For more information and a work-around, see (Xilinx Answer 30647)


6. There have been some attributes updates to the GTX wrappers since the core was released. For more information, see (Xilinx Answer 30577)


7. The GTX OOBDETECT_THRESHOLD_0 attribute has been update. For more information, see (Xilinx Answer 32261).

AR# 30144
Date 05/22/2014
Status Archive
Type General Article
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