This Answer Record contains the Release Notes for the LogiCORE Ethernet Statistics v2.5 Core, which was released in the ISE 10.1 Initial IP Update, and includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
- ISE 10.1i design tools support
- Virtex-5 FXT support
- Verilog VCS simulator support
- Tools do not correctly pick up RAMS group in constraint for Spartan3-DSP devices:
TIMESPEC "TS_stats_ref_to_host" = FROM "RAMS" TO "host_clock" 8000 ps DATAPATHONLY;
This has been fixed in 10.1 SP1. For more information, see (Xilinx Answer 30467).
- In 10.1 SimPrims the output of X_IDELAY is 'X' in VCS Verilog Simulation. For more information, see (Xilinx Answer 30646).
- In 10.1 SimPrim Post PAR timing simulation, the simulation does not always work as expected. For more information, see (Xilinx Answer 30815).