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AR# 30162

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) - Release Notes and Known Issues

Description

The DDS Compiler supersedes all previously released Xilinx Sine-Cosine Look-Up Table (Sin Cos LUT) cores, including the LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v5.0.

Please see (Xilinx Answer 29976) for a detailed list of LogiCORE DDS (Direct Digital Synthesizer) Compiler Release Notes and Known Issues.

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) Core.

The following information is listed for each version of the core:

- New Features

- Bug Fixes

- Known Issues

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) Lounge:

http://www.xilinx.com/products/ipcenter/Sine_Cosine_Look_Up_Table.htm

Solution

General LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) Issues

- N/A

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v5.0

Initial Release in ISE 6.3i IP Update 3

New Features

- Support added for Virtex-4 FPGA

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 21518) Why does Equation 3 in the data sheet quote a dynamic range of -2^(n-2) to +2^(n-2) -1 for the symmetrical case?

- (Xilinx Answer 30626) Why are there mismatches between the behavioral simulation and the post-translate simulation when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine Cosine LUT IP?

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v4.2

Initial Release in ISE 5.1i IP Update 1

New Features

- Support added for Spartan-3

- Re-architected for increased performance

- Symmetric output option added. An extra integer bit is used so that the effective output range is -1.0 to +1.0 instead of -1.0 to almost +1.0.

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 12596) Why does MAP fail with "ERROR:Pack:679 - Unable to obey design constraints."?

- (Xilinx Answer 30626) Why are there mismatches between the behavioral simulation and the post-translate simulation, when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine Cosine LUT IP?

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v4.1

Initial Release in ISE 4.2i IP Update 2

New Features

- N/A

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 12596) Why does MAP fail with "ERROR:Pack:679 - Unable to obey design constraints."?

- (Xilinx Answer 30626) Why are there mismatches between the behavioral simulation and the post-translate simulation when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine Cosine LUT IP?

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v4.0

Initial Release in ISE 4.1i IP Update 1

New Features

- Support added for Virtex-II Pro and Spartan-IIE

Bug Fixes

- Enhanced Verilog Warnings to include time and hierarchy information

Known Issues

- (Xilinx Answer 12596) Why does MAP fail with "ERROR:Pack:679 - Unable to obey design constraints."?

- (Xilinx Answer 30626) Why are there mismatches between the behavioral simulation and the post-translate simulation when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine Cosine LUT IP

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v3.0

Initial Release in ISE 3.3 IP Update 3

New Features

- Support added for Virtex-II

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 12599) 4.1i CORE Generator Sine/Cosine Lookup Table v3.0 is not generated when Block ROM is used

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v2.1

Initial Release in ISE 3.2 IP Update 2

New Features

- N/A

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 7441) "ERROR: Unable to find library for core Sine-Cosine_Look-Up_Table|Xilinx|xc4000_all"

- (Xilinx Answer 10463) After installing D_IP2, I cannot select the Sine-Cosine Look-UP Table for generation (4000 and Spartan families).

LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v2.0

Initial Release in ISE 3.1 IP Update 1

New Features

- Support for Spartan-II, Virtex, and Virtex-E

- User selectable option for table value storage in either Distributed or Block Memory

- Supports THETA input widths of 3 to 10 bits

- Supports output Sine/Cosine widths of 4 to 32 bits

- Automatically selects between quarter wave storage and full 360 degree wave storage for the most efficient implementation

- Variable pipelining options to improve overall clock rates

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 7128) Sine Cosine LUT module are missing in 2.1i CORE Generator tree

- (Xilinx Answer 9218) Why do I get "ERROR: End of source encountered before closing all `endif directives" when compiling sincos_v2_0.v?

AR# 30162
Date Created 03/13/2008
Last Updated 12/19/2009
Status Active
Type General Article