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AR# 30167

LogiCORE 3GPP Turbo Convolutional Code Encoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE 3GPP Turbo Convolutional Code Encoder Core.

The following information is listed for each version of the core:

- New Features
- Bug Fixes
- Known Issues

LogiCORE 3GPP Turbo Convolutional Code Encoder Lounge:

http://www.xilinx.com/products/ipcenter/DO-DI-TCCENC-UMTS.htm

Solution

General LogiCORE 3GPP Turbo Convolutional Code Encoder Issues

- N/A

LogiCORE 3GPP Turbo Convolutional Code Encoder v4.1

Initial Release in Vivado 2012.2
Supported Devices (Vivado)

- All Series 7 devices

New Features

-Vivado 2012.2software support

Bug Fixes

- None

Known Issues(ISE)

- N/A


Known Issues (Vivado)

-(Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with error Error: Failed to find design work <Core name>?


LogiCORE 3GPP Turbo Convolutional Code Encoder v4.0

Initial Release in ISE 11.2

New Features

- ISE 11.2 software support
- Virtex-6 and Spartan-6 support
- Removed ACLR pin. Use SCLR pin if reset is required.
- Removed support for Virtex-II and Virtex-II Pro.

Bug Fixes

- None

Known Issues

- N/A

LogiCORE 3GPP Turbo Convolutional Code Encoder v3.1

Initial Release in ISE 10.1

New Features

- Support added for Spartan-3A DSP

Bug Fixes

- CR 449449 Eliminated Inferred latch in Virtex-4 and Virtex-5 implementations
- CR 429948 XCD file corrected to allow support for Virtex-II Pro-X family
- CR 457480 Width of BLOCK_SIZE port on GUI symbol corrected

Known Issues

- N/A

LogiCORE 3GPP Turbo Convolutional Code Encoder v3.0

Initial Release in ISE 8.2i IP Update 2

New Features

- Support added for Virtex-5
- Trellis termination bits are now multiplexed by default onto three outputs over four cycles as specified by 3GPP TS 25.222 Para 4.2.3.2.2 (Parallel output of trellis termination bits is still available as an option)

Bug Fixes

- N/A

Known Issues

- N/A

LogiCORE 3GPP Turbo Convolutional Code Encoder v2.0

Initial Release in ISE 7.1i IP Update 1

New Features

- New, more efficient interleaver enables 40% area reduction over v1.0 implementation
- External RAM option added

Removed Features

- Single-buffered option removed

Bug Fixes

- Double buffering output now independent of FD (please refer to data sheet for details)

Known Issues

- N/A

LogiCORE 3GPP Turbo Convolutional Code Encoder v1.0

Initial Release in ISE 6.3i IP Update 4

New Features

- Implements 3GPP/UMTS Specifications
- Support for Spartan-2, Spartan-3, Virtex, Virtex-II, Virtex-II Pro, Virtex-4
- Full 3GPP block range supported, 40-5114
- Up to 16 simultaneous data channels
- Optional double-buffered symbol memory for maximum throughput
- Support for rate 1/3 or 1/5 coded inputs

Bug Fixes

- N/A

Known Issues

- N/A

AR# 30167
Date Created 03/11/2008
Last Updated 01/02/2013
Status Active
Type General Article
Tools
  • Vivado - 2012.2