UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30168

LogiCORE 3GPP2 Turbo Convolutional Code Decoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE 3GPP2 Turbo Convolutional Code Decoder core. 

 

The following information is listed for each version of the core: 

- New Features 

- Bug Fixes 

- Known Issues 

 

LogiCORE 3GPP2 Turbo Convolutional Decoder Lounge: 

http://www.xilinx.com/products/ipcenter/DO-DI-TCCDEC.htm


The 3GPP2 Turbo Convolutional Decoder core has been discontinued. Please see the Following PDN: 

http://www.xilinx.com/support/documentation/customer_notices/xcn14010.pdf

Solution

General LogiCORE 3GPP2 Turbo Convolutional Code Decoder Issues 

- N/A 

 

LogiCORE 3GPP2 Turbo Convolutional Code Decoder v2.1 rev1 

Initial Release in ISE 9.1i IP Update 2 

New Features 

- Support added for Spartan-3A DSP 

Bug Fixes 

- Same as v2.1 

Known Issues 

- Same as v2.1 

 

 

LogiCORE 3GPP2 Turbo Convolutional Code Decoder v2.1 

Initial Release in ISE 9.1i IP Update 1 

New Features 

- Support added for Virtex-4 and Virtex-5 devices  

- Support added for cdma2000 High Rate Packet Data Air Interface Specifications, '3GPP2 C.S0024-B V1.0' and '3GPP2 C.S0024-A V2.0'  

- Increased dynamic range supported with a 2-bit increase in the supported input integer and internal metric integer bit widths  

Bug Fixes 

- N/A 

Known Issues 

- N/A 

 

 

LogiCORE 3GPP2 Turbo Convolutional Code Decoder v1.0 

Initial Release in ISE 6.1i IP Update 1 

New Features 

- Support for Spartan-3, Spartan-3E, Virtex-II and Virtex-II Pro FPGAs 

- Implements the CDMA2000/3GPP2 specification 

- Core contains the full 3GPP2 interleaver 

- Full 3GPP2 block size supported, that is, 378-20730 

- Core implements the MAX*, MAX or MAX SCALE algorithms 

- Dynamically selectable number of Iterations 1-15 

- Number representation: twos compliment fractional numbers 

- Data input: 2 or 3 integer bits and 1 to 4 fractional bits 

- Internal Calculations: 6 or 7 integer bits and 1 to 4 fractional bits 

- Sliding window size of 32 or 64 

- Works with all 3GPP2 code rates 

- Internal or external RAM data storage 

Bug Fixes 

- N/A 

Known Issues 

- External memory ports are still present on output when "Use External RAM" check box is not used. 

See (Xilinx Answer 20792).

AR# 30168
Date Created 03/13/2008
Last Updated 04/02/2015
Status Active
Type General Article
Devices
  • Virtex-5