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AR# 30173

LogiCORE IP DVB-S2 FEC Encoder - Release Notes and Known Issues

Description

Keywords: ISE, Mobile, FEC,satellite

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP DVB-S2 FEC Encoder Core.

The following information is listed for each version of the core:
- New Features
- Bug Fixes
- Known Issues

LogiCORE IP DVB-S2 FEC Encoder Lounge:
http://www.xilinx.com/products/ipcenter/DO-DI-DVBS2-FEC-ENC.htm

Solution

General LogiCORE IP DVB-S2 FEC Encoder Issues
- Is there a C model for the DVB-S2 Encoder Core? See (Xilinx Answer 29688).


LogiCORE IP DVB-S2 FEC Encoder v2.0
New Features

- ISE 11.4 software support
- Virtex-6 and Spartan-6 device support
- Option added to increase output buffer size to maintain high throughput when frame size changed dynamically.
- Customer testbench that demonstrates how sustained frame throughput can be achieved with changing frame size.

Bug Fixes

- There are no resolved issues.

Known Issues

The following are known issues for v2.0 of this core at the time of release:

- CR534446 Warnings issued by the Verilog Unisim behavioral model saying that there is a U in an arithmetic operand.
- This occurs due to a arithmetic operation being performed on an unused input which is later discarded. It is an issue with the ISE software, rather than the core. This is scheduled to be fixed in ISE Design Suite 12.1.

- The work-around is to disable the warnings from the Synopsys Package.


LogiCORE IP DVB-S2 FEC Encoder v1.4
Initial Release in ISE
New Features
- ISE 10.1 software support
- Input format option to allow byte-wide input of MPEG data
- Output format option to provide encoded output as symbols
- Input buffer option to allow input data to be processed as soon as possible, thereby reducing number of cycles from input to output through the core.
Bug Fixes
- CR471366: SCLR overrides CE - inconsistent with other DSP cores


- CR471364: RFFD might go High when RFD is Low


- CR471365: RDY and FD_OUT gated by CTS - inconsistent with other DSP cores


- CR452807: Latch warning, WARNING:Xst:737 - Found 1-bit latch for signal <flush>

Known Issues
- Why does the DVB S2 FEC Encoder data sheet in the CORE Generator tool look incomplete. See (Xilinx Answer 31252).



LogiCORE IP DVB-S2 FEC Encoder v1.3
Initial Release in ISE
New Features
- Support added for Spartan-3A DSP device
- Addition of pilot and frame bits to rate input and output. Bits can be used for general purpose control signaling as data passes through the core.
Bug Fixes
- N/A
Known Issues
- N/A


LogiCORE IP DVB-S2 FEC Encoder v1.2
Initial Release in ISE 8.1i IP Update 1
New Features
- N/A
Bug Fixes
- CR 217360: Error in short frame BCH polynomial
- Spartan-3 FPGA data added to Core Performance in data sheet
Known Issues
- N/A


LogiCORE IP DVB-S2 FEC Encoder v1.1
Initial Release in ISE 7.1i I Update 3
New Features
- Modified CTS behavior for improved data flow in core
- Added timing diagrams to data sheet
Bug Fixes
- N/A
Known Issues
- Why is the output for the 1/4 rate short frame incorrect? See (Xilinx Answer 22099).


LogiCORE IP DVB-S2 FEC Encoder v1.0
Initial Release in ISE 7.1 IP Update 1
New Features
- Support for Spartan-3, Spartan-3E, Virtex-II, Virtex-II Pro, and Virtex-4 devices
- Forward Error Correction for DVB-s.2 (Compatible with ETSI EN 302 307 V1.1.1)
- Normal and short frames
- All code rates
- Input and output bugger
- BCH outer coding
- LDPC encoder and bit-interleaver
Bug Fixes
- N/A
Known Issues
- N/A




AR# 30173
Date Created 03/12/2008
Last Updated 11/29/2009
Status Active
Type General Article