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AR# 30177

LogiCORE Reed Solomon Encoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE Reed Solomon Encoder Core.

The following information is listed for each version of the core:

- New Features
- Supported Devices
- Resolved Issues
- Known Issues

For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General LogiCORE Reed Solomon Encoder Issues

LogiCORE Reed Solomon Encoder v8.0

Initial Release in ISE 13.4 software

New Features

- ISE 13.4 software support
- AXI interface added to core

Supported Devices

  • Zynq-7000*
  • Virtex-7 XC XT/HT/T
  • Virtex-7 -2L XC XT/T
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Kintex-7 XC
  • Kintex-7 -2L XC
  • Artix-7 XC
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XQ LX
  • Spartan-6 -1L XC LX

Resolved Issues

-None


Known Issues (ISE)

- None

Known Issues (Vivado)

- (Xilinx Answer 52206) Why do I get an Application Error when trying to synthesize using 2012.2 Vivado Synthesis?


LogiCORE Reed Solomon Encoder v7.1

Initial Release in ISE 12.2

New Features

- ISE 12.2 software support
- Support returned for Spartan(TM)-6 devices

Bug Fixes

- Spartan-6 family support added (Answer record AR 35676)


Known Issues

- None


LogiCORE Reed Solomon Encoder v7.0

Initial Release in ISE 11.2Software

New Features

- ISE 11.2 software support
- Virtex-6 and Spartan-6 support
- Asynchronous reset input removed
- Synchronous Clear input added. Use SCLR input for synchronous reset if required. Core does not need to be reset in normal operation.
- Reduced generation time

Bug Fixes

- None

Known Issues

-Why does the RS Decoder core (v7.0) not support Spartan-6 FPGA in 12.1? See (Xilinx Answer 34853).

LogiCORE Reed Solomon Encoder v6.1

Initial Release in ISE 9.1 IP Update 3

New Features

- Support added for Spartan-3A DSP devices
- New, easier to use GUI

Bug Fixes

- N/A

Known Issues

- N/A

LogiCORE Reed Solomon Encoder v6.0

Initial Release in ISE 8.2i IP Update 1

New Features

- Support added for Virtex-5
- Support added for ISE 8.2i
- Now uses XST to elaborate the design

Bug Fixes

- N/A

Known Issues

- When selecting "variable number of Check Symbols" with Reed Solomon Encoder why does it take a long time to generate the core? See (Xilinx Answer 25130).

LogiCORE Reed Solomon Encoder v5.0 r1

Initial Release in ISE 8.1i IP Update 1

New Features

- Support has been added for generating a Verilog simulation model using the "Structural" option

Bug Fixes

- To generate a Verilog simulation model select the "Structural" Box from the "Generation" Tab on the "Project>Project Options" menu

Known Issues

- Same v5.0

LogiCORE Reed Solomon Encoder v5.0

Initial Release in ISE 6.2i IP Update 2

New Features

- Support added for Virtex-4
- Support added for variable number of check symbols
- Support added for implementation architectures for the check symbol generator

Bug Fixes

- N/A

Known Issues

- Why is there an enable Pin on the GUI Symbol, but no option to chose the enable? See (Xilinx Answer 19526).

LogiCORE Reed Solomon Encoder v4.1

Initial Release in ISE 6.1i IP Update 1

New Features

- Option for variable N input
- Support for multi-channel mode
- Support added for ITU J.83 Annex B specification
- True clock enable
- New handshaking signals - ND, RDY, RFFD, RFD
- Speed/Area Optimization parameter removed. Now defaults to Speed optimization
- "Enable" input has been removed. Please use either ND or CE instead.

Bug Fixes

- N/A

Known Issues

- N/A

LogiCORE Reed Solomon Encoder v4.0

Initial Release in ISE 5.2i IP Update 2

New Features

- Support added for Spartan-3
- Supports new license-based enhanced full system evaluation flow

Bug Fixes

- N/A

Known Issues

- Why do I get a PAR warning about the placement constraints when the "Create RPM" option is selected? See (Xilinx Answer 16931).

LogiCORE Reed Solomon Encoder v3.0

Initial Release in ISE 4.2i IP Update 2

New Features

- Support added for Virtex-II Pro and Spartan-IIE

Bug Fixes

- N/A

Known Issues

- N/A

LogiCORE Reed Solomon Encoder v2.0

Initial Release in ISE 3.3 IP Update 4

New Features

- Fully synchronous design using a single clock
- Supports continuous output data with no gap between code blocks
- Symbol width from 3 to 12 bits
- Code block length variable up to 4095 symbols with up to 256 check symbols
- Supports shortended codes
- Supports any primitive field polynomial for a given symbol width
- User-configurable generator polynomial

Bug Fixes

- N/A

Known Issues

- Placer does not obey RPM constraints in a Reed-Solomon core. See (Xilinx Answer 11506).
- Reed Solomon Encoder and Decoder cores do not list Spartan-II as a supported device. See (Xilinx Answer 11340).
- ERROR:" Could not locate Project core xilinx_reed-solomon_decoder|xilinx|virtex+xc4000+spartan|1.0" See (Xilinx Answer 11238).

Linked Answer Records

Child Answer Records

AR# 30177
Date Created 03/13/2008
Last Updated 02/18/2013
Status Active
Type General Article
IP
  • Reed-Solomon Encoder