AR #30187 - LogiCORE 10-Gigabit Ethernet MAC v8.4 and earlier - After going full, RX FIFO stays full
LogiCORE 10-Gigabit Ethernet MAC v8.4 and earlier - After going full, RX FIFO stays full
| AR# | 30187 |
| Topic | IP-DS-10 Gigabit Ethernet MAC |
| Last Modified | 2008-04-23 00:00:00.0 |
| Status | Active |
Description
Keywords: XGMAC, 10, Ten, known, issues, release, notes, patch, installation, instruction, v8.4
In the 10-Gigabit Ethernet MAC v8.4 and earlier (when using the example design RX FIFO), if the FIFO is filled until the FULL flag goes high, even after frames are read from the FIFO the RX FIFO remains FULL and cannot be written to.
Solution
The issue can be fixed by modifying two lines in the rx_fifo.v/vhd file.If using Verilog in rx_fifo.v:
1. Remove write enable from the generation of the read and write address difference. On line 485, change:
else if (wr_enable == 1'b1):
to just: else
2. Change line 528 from:
if (wr_addr_diff[addr_width-1:2] == 0 && wr_addr_diff[1:0] != 2'b00)
to:
if (wr_addr_diff[addr_width-1:3] == 0 && wr_addr_diff[2:0] != 3'b000)
If using VHDL in rx_fifo.vhd:
1. Remove write enable from the generation of the read and write address difference. On line 427, change:
elsif wr_enable = '1' then
to just:
else
2. Change line 469 from:
if wr_addr_diff(addr_width-1 downto 2) = 0 and wr_addr_diff(1 downto 0) /= "00" then
to:
if wr_addr_diff(addr_width-1 downto 3) = 0 and wr_addr_diff(2 downto 0) /= "000" then
This issue will be fixed in the next release of the 10GEMAC v8.5 in 10.1 IP Update2.