We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30211

ModelSim 6.3c - Unable to observe all the bus bits in a VCD simulation


I attempt to add a bus to a VCD using the "vcd add" command, but I observe only some bits of the bus. For example, I tried to add a 16-bit bus using the command "vcd add /testbench/uut/my_bus", but I can see only the two most significant bits when I load the VCD.  


How can I resolve this problem?


This issue does not apply to situations where "vcd add" is not used. To work around this issue, add "-nopartialatomic" switch to the vsim command line. For example: 


vsim -nopartialatomic -do make_power_vcd.do 


This issue will be resolved in a future release of ModelSim.

AR# 30211
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked