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AR# 30220

9.2i EDK - When I increase the IPLB1 / DPLB1 clock frequencies, the design fails to operate

Description

When I increase the IPLB1 / DPLB1 clock frequencies, the design fails to operate. How can I increase the clock frequency and still have my design operate?

Solution

The frequency change needs to happen to the parameter C_FASTEST_PLB_CLOCK which is found in the MHS.

AR# 30220
Date Created 02/07/2008
Last Updated 05/20/2014
Status Archive
Type General Article