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AR# 3029

CONCEPT-HDL 13.5 - In a mixed-flow, Xilinx primitives are listed in the "resource file".


Keywords: Concept-HDL, Synplify, mixed-flow, primitives

Urgency: Hot

General Description:
The Cadence project manager delivered with Concept-HDL 13.5
(and, earlier versions) lists Xilinx primitives in the "resource file"
list of Synplify in a mixed-flow environment.


Concept-HDL is integrated with Synplicity's Synplify for design synthesis. In
mixed-level design methodology, Concept-HDL writes Verilog and VHDL
directly from a block diagram schematic. In the PE 13.5, the entire design is
netlisted and passed to Synplify; however, Xilinx primitives are listed in the
"resource file" list of Synplify, which conflicts with the synthesis library definition
of the primitive.

There are 2 issues to notice:

1. Synplify is not able to find declarations for the primitives that are in the
schematic Verilog file, as Concept-HDL provides them in all lower case.

2. Synplify will synthesize these behavioral models of the primitives.

This is corrected in PE 13.6. In the PE 13.6 release, there will be no netlisting
of these primitives for the purpose of going into Synthesis. This provides for
individual synthesis of the HDL blocks and EDIF netlisting of each of the
schematic blocks, as well as the ability to use a previously generated EDIF view
for blocks, rather than requiring a Verilog, VHDL or schematic view.
AR# 3029
Date Created 08/31/2007
Last Updated 02/08/2001
Status Archive