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AR# 30290

10.1 ISE - Known Issues for Project Navigator 10.1


This Answer Record lists the Known Issues for Project Navigator 10.1. Each Known Issue includes a link to another Answer Record that contains additional information on the issue.


Outstanding Known Issues in ISE 10.1.03

(Xilinx Answer 9186) - The Refresh button does not update open Language Templates window with IP core templates
(Xilinx Answer 12069) - Drag-and-drop of language templates does not work in Project Navigator on a UNIX platform
(Xilinx Answer 12081) - Synplify flows do not support schematic sources
(Xilinx Answer 17498) - Project Navigator CPLD Fitter reports require Mozilla directory to point to the JRE on Linux platform
(Xilinx Answer 17835) - ABEL test vectors do not appear in the Sources window if the "DEVICE" keyword is used in the ABEL file
(Xilinx Answer 17995) - Multiple sets of ABEL test vectors do not show up as Project Sources
(Xilinx Answer 17998) - File -> Save Project As... does not copy EDK project (".xmp" file) directory to new project location
(Xilinx Answer 20480) - Project Navigator does not display hierarchy for modules with circular hierarchy references
(Xilinx Answer 21387) - An IP core created using Project -> New Source is not added to the Project Navigator project if the name of the core is changed in the core customization GUI
(Xilinx Answer 21913) - Project Navigator does not include entity in project hierarchy if the entity name contains a dash
(Xilinx Answer 22886) - Some processes require Project Navigator to close before releasing memory
(Xilinx Answer 23522) - Editing an 'include file does not reset source hierarchy or process status
(Xilinx Answer 23448) - Remote Verilog files added through Tcl command are not found until the project is closed and re-opened
(Xilinx Answer 23521) - Project Navigator incorrectly parsers EDIF file with uppercase module names
(Xilinx Answer 23536) - Project Navigator incorrectly states that only one State Diagram (.dia) file may be added to a project
(Xilinx Answer 24465) - Project Navigator does not display hierarchy correctly for large HDL files
(Xilinx Answer 25233) - Implementation processes disappear for ABEL design if the device family is changed
(Xilinx Answer 25490) - Project Navigator incorrectly builds the hierarchy of some Verilog designs
(Xilinx Answer 29801) - All project sources are analyzed even if not in the selected hierarchy
(Xilinx Answer 30593) - Project Navigator attempts to overwrite symbol for a State Diagram (.dia) if the HDL is regenerated
(Xilinx Answer 30598) - Project Navigator might not update status correctly after a process has been forced "Up to Date"
(Xilinx Answer 30601) - Rapid switching between reports while the CPLD Fit report is updating causes Tcl error
(Xilinx Answer 30614) - Selecting Finish multiple times when creating a new project can result in a warning that the project is out of date
(Xilinx Answer 30618) - Project Navigator preferences are not saved when $HOME/.qt directory does not have Write permission
(Xilinx Answer 30619) - Changing project properties after forcing multiple processes up-to-date causes Internal error
(Xilinx Answer 30638) - Adding HDL source to project incorrectly marks process status as out-of-date
(Xilinx Answer 30657) - Back-Annotate Pin Locations requires user to set the property "Target UCF File Name" property
(Xilinx Answer 30662) - Virtex-5 and Spartan-3A Xilinx schematic macros are shown as "?" in Project Navigator source hierarchy
(Xilinx Answer 30665) - Applying the Balanced/Xilinx Default Design Strategy resets all properties including Macro Search Path and Verilog Include Directory
(Xilinx Answer 30683) - The .ise file stored in the <project name>_ise10migration.zip file is touched during migration
(Xilinx Answer 30818) - Project Navigator/Precision integration is not support on Vista platform
(Xilinx Answer 30891) - Project Navigator (_pn.exe) crashes on startup using Windows Vista Business Service Pack 1 64-bit
(Xilinx Answer 30961) - Design Summary does not show Module Level Utilization for migrated projects

Known Issues Resolved in ISE 10.1 Service Pack 1 (10.1.01)

(Xilinx Answer 22886) - (Partial fix) Some processes require Project Navigator to close before releasing memory
(Xilinx Answer 30194) - Running an XPS design in Project Navigator error: "WARNING:MDT - This flow has been removed ..."
(Xilinx Answer 30376) - Generate Tcl Script fails for Spartan-3A and Spartan-3AN designs
(Xilinx Answer 30599) - FPGA Editor -> "Open Without Updating" does not work if design is not fully routed
(Xilinx Answer 30611) - Apply Project Properties fails if a READ ONLY v9.2i .ise file is used
(Xilinx Answer 30617) - Editing a Design Strategy after switching between Virtex-4 device families causes "Fatal Error"
(Xilinx Answer 30641) - Timing Simulation with ISIM fails on CPLD designs - TOE error
(Xilinx Answer 30645) - The UUT appears undefined for Simulate Post-Place & Route Model process
(Xilinx Answer 30849) - Newly created source files do not appear in the Project Navigator Source window
(Xilinx Answer 30852) - VHDL design with packages error: "TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "0"'"
(Xilinx Answer 30853) - MATLAB must be closed after "Manage System Generator DSP Design" in order to run other processes
(Xilinx Answer 30854) - Manage System Generator DSP design error: "ERROR:ProjectMgmt:387 - TOE: ITclInterp ..."
(Xilinx Answer 30855) - New Strategy Editor is not reading property values from XDS files
(Xilinx Answer 30857) - Synthesis fails when a partition is placed on a System Generator module
(Xilinx Answer 30858) - Project Migration fails if Source files are missing
(Xilinx Answer 30861) - New Project Wizard freezes if the "Finish" button is selected twice
(Xilinx Answer 30862) - Opening NGC or NGR for schematic view fails using File -> Open instead of PN process
(Xilinx Answer 30863) - Status incorrect when Synthesis fails on design with an XMP source
(Xilinx Answer 30864) - Deleted constraints are still honored until project is closed
(Xilinx Answer 30865) - "Set As Top Module" does not work on System Generator Module
(Xilinx Answer 30866) - Status is incorrect for failed Synplify process
(Xilinx Answer 30867) - Snapshot created from the "Restore Snapshot" process cannot be opened
(Xilinx Answer 30868) - The .restore script does not contain references to System Generator project
(Xilinx Answer 30870) - Running SmartGuide and MPPR generates PAR and ProjectMgmt errors
(Xilinx Answer 31080) - Project Navigator gives segmentation Fault on startup when run over x-server

Known Issues Resolved in ISE 10.1 Service Pack 2 (10.1.02)

(Xilinx Answer 25515) - Unable to launch GDB, the following error occurs: "Tk_Init failed: Can't find a usable tk.tcl in the following directories:"
(Xilinx Answer 30474) - Running ChipScope Core Inserter or analyzer from ISE results in "Error: Unable to find ChipScope Exe at <File Path>"
(Xilinx Answer 30655) - Saving Generate Tcl script to remote location results in bad name and path
(Xilinx Answer 30667) - Migrating an EDIF project from ISE 8.x to ISE 10.1 fails
(Xilinx Answer 30795) - My EDK project is not recognized inside my ISE project; "WARNING: there is no XPS project associated with this design"
(Xilinx Answer 31205) - Stopping a process in Project Navigator does not terminate the underlying application
(Xilinx Answer 31213) - Project Navigator process window does not reflect error status for ERROR:Route:472
(Xilinx Answer 31214) - Project Navigator asks me to migrate a project that was created using the same version
(Xilinx Answer 31215) - Project Navigator closes unexpectedly when saving top level source file with invalid component instantiation
(Xilinx Answer 31217) - Migrating an ISE 8.x project to ISE 10.1 on Linux causes a segmentation fault
(Xilinx Answer 31218) - Adding an EDIF (.edn) file with partitions causes Project Navigator to fail
(Xilinx Answer 31219) - Project Navigator fails to process design containing System Generator module on Window Vista
(Xilinx Answer 31220) - Running create_partitions or create_libraries procedures from a Generated Tcl Script closes the project
(Xilinx Answer 31224) - Project Navigator: Project -> Generate Tcl Script process fails if spaces are in the specified file name
(Xilinx Answer 31225) - Sourcing a Project Navigator Generated Tcl script returns: can't read "myScript": no such variable
(Xilinx Answer 31226) - Project Navigator "Generate IBIS Model" process does not run

Known Issues Resolved in ISE 10.1 Service Pack 3 (10.1.03)

(Xilinx Answer 23469) - Project Navigator incorrectly adheres to "synopsys translate_off" directive anywhere in commented text
(Xilinx Answer 25234) - The Project Navigator Create Schematic Symbol process fails for ABEL files
(Xilinx Answer 29629) - Synopsys translate_off directive in text comments can cause "No Design Unit ..." error
(Xilinx Answer 30039) - Project Navigator does not properly handle multiple files with the same name in different HDL libraries
(Xilinx Answer 30562) - A space in Custom Editor directory path prevents ISE 9.2i project from opening in ISE 10.1
(Xilinx Answer 30663) - Cleanup Project File process deletes user NGC files manually copied to project directory
(Xilinx Answer 30677) - System Generator files not allowed as a top level source
(Xilinx Answer 30861) - Project Navigator New Project Wizard freezes if the Finish button is selected twice
(Xilinx Answer 31168) - HDL Instantiation Template requires "Rerun All" for IP cores if the template has not previously been generated
(Xilinx Answer 31218) - Adding an EDIF (.edn) file with partitions causes Project Navigator to fail
(Xilinx Answer 31304) - Project Navigator sends incorrect top level module to synthesis for schematic design
(Xilinx Answer 31637) - XMP submodules not handled correctly in Synplify Pro flow
(Xilinx Answer 31642) - Generate Programming File Process causes BitGen after "force status up-to-date"
(Xilinx Answer 31651) - Project Migration fails if directory of source file contains spaces
(Xilinx Answer 31652) - Project Navigator silently changes the project device if current project device is not installed
(Xilinx Answer 31653) - Timing report process fails for CoolRunner2 projects
(Xilinx Answer 31660) - Running "Simulate Post-Place & Route Model" process on SysGen design fails to create .vcd file
(Xilinx Answer 31659) - Simulate Behavioral Model fails for ABEL designs when using ModelSim
AR# 30290
Date Created 03/27/2008
Last Updated 02/24/2012
Status Archive
Type Known Issues