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AR# 30291

10.1 CORE Generator - Known Issues for CORE Generator 10.1

Description


This Answer Record contains a list of known issues involving CORE Generator in the ISE 10.1 Release.



For IP-specific information, see the Xilinx IP Web page at:

http://www.xilinx.com/ipcenter

Solution


Current Known Issues

(Xilinx Answer 19597) - Schematic symbol files are not automatically created for many of the larger IP cores

(Xilinx Answer 20478) - A CORE Generator project created on a PC does not behave properly on Linux and Solaris systems

(Xilinx Answer 20780) - CORE Generator - "ERROR:coreutil:195 - Could not create Java virtual machine"

(Xilinx Answer 21101) - Memory Editor always sets Memory_initialization_radix in COE is set to two

(Xilinx Answer 21236) - Some IP do not show generation status after recustomizing

(Xilinx Answer 21955) - An error occurred while running Java. This might be due to memory limitations

(Xilinx Answer 22549) - When running Manage Cores through Project Navigator on Linux 32, IP cores cannot be customized when Java memory is set to 2048 or above

(Xilinx Answer 22583) - Dual Port Block Memory v6.3 - "Show Coefficients" does not display the content of the COE file if the depth is greater than 511

(Xilinx Answer 22601) - Fragmented or incomplete error messages are displayed in the CORE Generator console window

(Xilinx Answer 23688) - Core Customization GUI does not open on Linux when the project directory is in "$Xilinx"

(Xilinx Answer 24113) - Linear Feedback Shift Register GUI opens as a blank window with some window resolutions

(Xilinx Answer 24389) - Tab outlines of the IP views (View by function/name/Generated) are not visible on Windows XP64

(Xilinx Answer 25237) - Running CORE Generator in batch mode over an X server connection requires DISPLAY variable

(Xilinx Answer 25370) - Generation fails if CORE Generator is launched from a directory relative to project directory on Linux OS

(Xilinx Answer 29260) - "ERROR:coreutil - Portability:74" when generating a LogiCORE Aurora Core v2.7

(Xilinx Answer 30527) - Resource Utilization is not available for multi-netlist IP cores

(Xilinx Answer 30535) - Text disappears on FIR Compiler v3.2 graph when COE file is loaded

(Xilinx Answer 30542) - Incorrect VHO file created for Reed/Solomon Decoder when no license is found



Issues fixed in ISE 10.1 SP1

(Xilinx Answer 30196) - Invalid speed grade causes error: "ERROR:sim - NgdBuild:15 - Missing "-p" option and no target architecture available!"

(Xilinx Answer 30515) - White space in project directory causes error: "ERROR:coreutil - Failure to generate output products" for specific IP cores

(Xilinx Answer 30528) - CIC and FIR Filter graphs do not display properly on Windows NT64, Vista64

(Xilinx Answer 30613) - Serial RapidIO core cannot be generated over a Linux Samba mount

(Xilinx Answer 30856) - ChipScope core is not created if EDIF is selected as netlist output type
AR# 30291
Date Created 03/13/2008
Last Updated 07/28/2010
Status Archive
Type General Article