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AR# 30306

Spartan-3/Spartan-3E/-3A DCM - What is the LOCK behavior of the DCM? Should other signals be monitored?


The CLKIN to my DCM may stop, wander, or have excess Jitter. Will the LOCK output go low to show this or should other signals be monitored?


This Answer applies to Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, and Spartan-3A DSPFPGAs

If CLKIN has the possibility to stop, wander, or have excess Jitter, the LOCK signal in a Spartan-3E/-3A device may not go low. The LOCK output is to indicate when the DCM outputs are valid. In some cases it may not go LOW to indicate the DCM has lost lock.

Monitoring Status bit 1 is recommended as this will indicate when the CLKIN has stopped (moved outside the acceptable CLKIN tolerances). The STATUS(1) is not a sticky bit; that is, it will go low once the CLKIN has returned. For the most robust indicator of the status of your DCM's output clock, monitoring both the LOCK and STATUS(1) bits is recommended.

Here is additional information regarding the output clock signals relative to the input clock of the DCM:

When the input clock is being stopped (CLKIN remains High or Low for more than 1 clock cycle), one to eight more output clock cycles are still generated as the delay line is flushed. When the output clock stops, the CLKIN stopped (STATUS(1)) signal is asserted. When the clock is restarted, the output clock cycles are not generated for one to eight cycles while the delay line is filled. Similarly, the STATUS(1) signal is de-asserted once the output clock is generated.

For more information on the Spartan-3E/-3A DCMs, please see the Spartan-3 Generation FPGA User Guide:

AR# 30306
Date Created 02/21/2008
Last Updated 02/22/2013
Status Active
Type General Article
  • Spartan-3E
  • Spartan-3A
  • Spartan-3AN
  • Spartan-3A DSP
  • Digital Clock Manager (DCM) Module