| AR# |
30308 |
| Part |
SW-SysGen |
| Last Modified |
2008-04-21 00:00:00.0 |
| Status |
Active |
| Keywords |
.do, ISE, generate testbench, SysGen |
Description
Keywords: .do, ISE, generate testbench, SysGen
When I run a simulation with my System Generator project in ISE, the automatically generated stimulus, testbench files, and custom ".do" files are not used if Verilog is my HDL language.
Solution
This is a known issue in System Generator 10.1. The ISE project file does not enable the System Generator created custom ".do" files for simulation.
These files are still created and can be specified for simulation by selecting process properties for the simulation process you want to run, and specifying the applicable ".do" script that has been generated to the HDL Netlist directory.
Note that this issue affects only Verilog designs; this issue will be resolved in a future release.
For a list of all System Generator for DSP known issues, see
(Xilinx Answer 29595).
