We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30308

10.1.01 System Generator for DSP - Why does my simulation not use the automatically generated Verilog testbench and stimulus files?


When I run a simulation with my System Generator project in ISE, the automatically generated stimulus, testbench files, and custom ".do" files are not used if Verilog is my HDL language.


This is a known issue in System Generator 10.1. The ISE project file does not enable the System Generator created custom ".do" files for simulation. 


These files are still created and can be specified for simulation by selecting process properties for the simulation process you want to run, and specifying the applicable ".do" script that has been generated to the HDL Netlist directory. 


Note that this issue affects only Verilog designs; this issue will be resolved in a future release. 


For a list of all System Generator for DSP known issues, see (Xilinx Answer 29595).

AR# 30308
Date Created 02/21/2008
Last Updated 05/22/2014
Status Archive
Type General Article