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AR# 30312

10.1.00 - System Generator for DSP - I am able to generate my model using the DCM option for "Multirate Implementation" despite having blocks in my design that are listed as unsupported for the DCM

Description

Why am I able to generate my model using the DCM option for "Multirate Implementation" despite having blocks in my design that are listed as unsupported for the DCM?

Solution

This is a known issue in System Generator 10.1.00 for several blocks. The following Sysgen Blocks will not work with the new Multirate DCM implementations; however, SysGen does not issue a DRC error when these blocks are encountered in the design:

1) Downsample Block: First value of Frame

2) Upsample Block: Insertion of Zeroes

3) Time Division Multiplexer

4) Time Division DeMux

5) Parallel to Serial with latency = 0

6) ce_probe

7) clk_probe

8) FIR Compiler: Core rate != Input Sample rate

If you wish to use the DCM option for your "Multirate Implementation" you should not use the blocks listed.

For a listing of all known issues pertaining to System Generator for DSP see (Xilinx Answer 29595).

This will be resolved in a future System Generator release.

AR# 30312
Date Created 02/21/2008
Last Updated 12/15/2012
Status Active
Type General Article