LogiCORE RapidIO - Virtex-4: x4 Core might train down to x1 intermittently as a resulf of an MGT synchronization issue
Description
Keywords: endpoint, serial, high, speed, high-speed, PHY, logical, design environment, SRIO, RIO, rapid, rapidio, IO, MGT, GT11, CORE, Generator, physical, logicalio, transport, buffer, mgt, rxlock, txlock, refclk, usrclk, synchronization, reset
In Virtex-4, the x4 Core might intermittently train down to x1 mode. The root cause of this is that the TXLOCK and RXLOCK signals coming from MGT go into the oplm_pma_pcs_rst_sequence.v module and they are not synchronized to the uclk domain.
Tables A-6 and A-7 of the Virtex-4 RocketIO MGT User Guide incorrectly claim that RXLOCK and TXLOCK are synchronous to USRCLK; however, TXLOCK and RXLOCK are actually synchronous to REFCLK as they are sourced from the Frequency Detector. There is no guarantee that USRCLK or USRCLK2 will be toggling by the time RX/TXLOCK asserts. This issue can potentially put SRIO state machine to an unknown state, causing certain MGT lanes to fail.
This issue is applicable to Virtex-4 only. Virtex-5 or Virtex-II Pro is not subject to this issue.
Solution
SRIO v4.4 Core (tentatively scheduled for late in May 2008) will be updated to address this issue. If you are using SRIO v4.1, v4.2, or v4.3, please use the work-around described below. If you are using SRIO v3.1 Core, please contact Xilinx Technical Support to obtain a patch.To work around this issue, synchronize TXLOCK and RXLOCK by running each of them through two registers clocked by the SRIO uclk. This can be done in the "oplm_pma_pcs_rst_sequence.v" module as follows:
Go to Example Design directory and change all occurrences within the "oplm_pma_pcs_rst_sequence.v" file (except the port assignments) from TXLOCK and RXLOCK to txlock_qq and rxlock_qq respectively. Next, place this code snippet in the oplm_pma_pcs_rst_sequence below the "//Internal signal declarations" tag:
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reg txlock_q, txlock_qq;
reg rxlock_q, rxlock_qq;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
txlock_qq <= #FFD 1'b0;
txlock_q <= #FFD 1'b0;
rxlock_qq <= #FFD 1'b0;
rxlock_q <= #FFD 1'b0;
end else begin
txlock_qq <= #FFD txlock_q;
txlock_q <= #FFD TXLOCK;
rxlock_qq <= #FFD rxlock_q;
rxlock_q <= #FFD RXLOCK;
end
end
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