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AR# 30316

10.1.01 System Generator for DSP - Why do I get mismatches in my post-translate, post-MAP, or post-PAR simulation if I use the DCM for my "Multirate Implementation"?

Description

Why do I get mismatches in my post-translate, post-MAP, or post-PAR simulation if I use the DCM for my "Multirate Implementation"? 

 

ModelSim reports errors as follows: 

 

"# ** Data mismatch on instance dcm_case1_gateway_out at time 785 ns. 

 # Simulink result: 0b0000000000000. (0.000000e+000) 

 # VHDL result: 0b1111111111111. (-1.000000e+000)"

Solution

This issue does not affect hardware. These designs have been verified in hardware using ChipScope to have correct behavior. This is a known issue with gate level simulations of System Generator designs generated with DCM chosen for "Multirate Implementation".  

 

This issue will be resolved in a future System Generator release.

AR# 30316
Date Created 03/14/2008
Last Updated 05/22/2014
Status Archive
Type General Article