If my design does not use the full rate system clock and the DCM option is used for "Multirate Implementation," I get mismatches in my behavioral simulation.
This is a known issue caused by the fact that the testbench is driven by the full speed system clock even though the fastest clock used in the design is slower. This causes mismatches in behavioral simulation.
You can work around this issue by adding "dummy" registers to your design which run at the full system rate.
This issue will be resolved in a future release of System Generator.
For a listing of all System Generator for DSP known issues, see (Xilinx Answer 29595).