Main
Home  :  Support  :  Answers  :  LogiCORE RapidIO - Re-initialization is not forced following a change to Port Width Override

LogiCORE RapidIO - Re-initialization is not forced following a change to Port Width Override

AR# 30323

Search For Another Answer
Topic IP-RapidIO-Serial
Last Updated 02/22/2008
Status Active
Description

Keywords: endpoint, serial, high, speed, high-speed, PHY, logical, design environment, SRIO, RIO, rapid, rapidio, IO, MGT, 10.1, I/O, CORE, Generator, physical, logicalio, transport, buffer, mgt, vio, xviodemo, re-init, re-initialize

Changing the Port Width Override value in the Port n Control CSR (0x5C) should force re-initialization to change to the requested size. However, this does not currently happen.

Solution

This issue will be addressed in SRIO v4.4, expected for release in late May 2008.

If you need a patch for this sooner, please open Xilinx Technical WebCase at
http://www.xilinx.com/support/clearexpress/websupport.htm
Please have the Technical Support Engineer contact the RapidIO core expert.
 
 
/csi/footer.htm