We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30330

10.1 EDK, MPMC v4.00.a - MPMC SDMA timing diagrams are incorrect


In the SDMA PIM section of the SDMA data sheet, the following figures are copies of other figures: 


- Page 86, Figure 27 Receive Data Write is incorrect. It is a copy of Figure 26. 

- Page 87, Figure 29 Receive LocalLink Timing is incorrect. It is a copy of Figure 28. 


What are the correct diagrams?


This issue is planned to be fixed in the newest MPMC core data sheet, starting with EDK 10.1, Service Pack 1.

AR# 30330
Date Created 02/22/2008
Last Updated 05/22/2014
Status Archive
Type General Article