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AR# 30355

10.1 PAR - Overview of new behavior where XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING variable is replaced by the CLOCK_DEDICATED_ROUTE constraint

Description


Changes in placer behavior:

In ISE 10.1, a change has been made to how the Placer handles the error condition that a clock IOB component is not placed at an optimal dedicated clock IOB site. In 9.2i, if the nonoptimal clock IOB placement was desired, it was necessary to set an environment variable to change the error condition to a warning. This variable overrides all possible errors of this type, not just the specific condition that had been deemed acceptable. In 10.1, instead of setting a variable, it is possible to apply a pin constraint to override these errors specifically. The error message contains the recommended constraints to be used to override the error. The variable no longer functions in 10.1.

Example of 9.2i behavior:
"ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The clock IOB component <clocks_1_src_clk1> is placed at site AD17. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue."

Example of 10.1 behavior:
"ERROR:Place:1018 - A clock IOB / clock component pair have been found that are
not placed at an optimal clock IOB / clock site pair. The clock component
<fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG> is placed at site
<BUFGMUX_X2Y10>. The IO component <fpga_0_Ethernet_MAC_PHY_rx_clk_pin> is
placed at site <AA14>." This will not allow the use of the fast path between
the IO and the Clock buffer. If this sub-optimal condition is acceptable for
this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf
file to demote this message to a WARNING and allow your design to continue.
However, the use of this override is highly discouraged as it may lead to
very poor timing results. It is recommended that this error condition be
corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the
.ucf file to override this clock rule.
< PIN "fpga_0_Ethernet_MAC_PHY_rx_clk_pin.DELAY_ADJ.IBUF_OUT"
CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG.GCLKMUX.I0"
CLOCK_DEDICATED_ROUTE = FALSE; >

Solution


Overview of "ERROR:Place:645" and "ERROR:Place:1018" errors:

Nonoptimal clock placements can occur for three reasons:

- User constraints lock clock components to a nonoptimal configuration. These errors occur most frequently as a result of user constraints; typically, clock IOBs locked to nondedicated clock IOBs. This is often caused by a misconception about which IOB sites are dedicated clock IOB sites. A common mistake is using the N-side of a "GC" IOB pair for a single-ended clock input. Only the P-side can be used for this purpose (i.e., IO_L1P_GC_LC_4 can be used, but IO_L1N_GC_LC_4 cannot). Another mistake is assuming that all "CC" clock capable pins can be used for global clocks. A "GC" pin must be used to avoid the nonoptimal clock placement errors.

- Automatic placement uses non-optimal placement because an optimal placement is not available. If an optimal clock placement is not possible, the placer will produce a non-optimal placement rather than no placement.The design can be examined to determine whether the additional delays resulting from non-optimal placement are acceptable or whether a design change is possible to accommodate an optimal clock placement.

- Automatic placement uses non-optimal placement, even though an optimal placement is available. This condition is considered a placement bug and should be reported to Xilinx Support. This is an area of quality focus and test cases that reproduce this failure are welcome. Please open a WebCase and reference this statement.

If the non-optimal placement and the associated delay is deemed to be acceptable, the error can be reduced to a warning by adding the PIN constraints contained in the message to your UCF file. For the example message above, the UCF syntax is:

PIN "fpga_0_Ethernet_MAC_PHY_rx_clk_pin.DELAY_ADJ.IBUF_OUT" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG.GCLKMUX.I0" CLOCK_DEDICATED_ROUTE = FALSE;

NGDBuild errors when using CLOCK_DEDICATED_ROUTE constraints suggested by the placer:

Cases have been seen where the pin name suggested for the CLOCK_DEDICATED_ROUTE constraint is incorrect as a result of a failure to correctly back-annotate to a valid logical instance name. The placer typically suggests two pins for use with the constraint, either of which can be used alone to override the error. If one of the pin constraints is not recognized by NGDBuild, it can be removed and the other pin constraint can be used.

"ERROR:ConstraintSystem:59 - Constraint <PIN "instance_name/CLKOUT0_BUFG_INST.I0"
CLOCK_DEDICATED_ROUTE ...> [top.ucf(6)]: PIN
"instance_name/CLKOUT0_BUFG_INST.I0" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file."
AR# 30355
Date Created 02/24/2008
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 12.1