We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30390

10.1i MAP WARNING:LIT:243 - Logical network CLK_IBUF has no load -Startup_spartan2 is correctly connected in my design


I receive the following MAP warning when I implement a design with Startup_spartan2:

Logical network CLK_ IBUF has no load.

However, in my design, the IBUF is connected to Startup_spartan2 and the component is correctly placed and routed. Can I ignore this warning?


This warning is incorrect and can be safely ignored.

In addition, you might receive the following warning:

WARNING:PhysDesignRules:812 - Dangling pin <GWE> on block:<STARTUP_SPARTAN_INST>:<STARTUP_STARTUP>.

This warning can also be safely ignored.

AR# 30390
Date Created 05/16/2008
Last Updated 12/15/2012
Status Active
Type General Article