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AR# 30449

12.1 Timing Analyzer - GTP - How is a PERIOD constraint on REFCLK passed through the GTP_DUAL tile?

Description

How is a PERIOD constraint on REFCLK passed through the GTP_DUAL tile? Is it automatically derived by every relevant output clock of the GTP_DUAL?

Solution


MGTCLKP and MGTCLKN are dedicated GTP reference clock inputs on the Virtex-5 LXT and SXT families. There are three ways to get to this clock in the FPGA fabric.

1. REFCLKOUT- This is an exact copy of the reference clock input to the GTP_DUAL column.

2. TXOUTCLK- This is a divided version of the serial PLL transmit clock. This clock is intended to drive the GTP-Fabric interface.

3. RXRECCLK- This is a divided version of the CDR that is synchronous to parallel incoming data. It is intended to be used for the receive GTP-Fabric interface in low-latency applications.


A PERIOD constraint placed on MGTCLKP or MGTCLKN will automatically propagate through to the REFCLKOUT port of the GTP_DUAL.

A PERIOD constraint placed on MGTCLKP or MGTCLKN will NOT propagate through to the TXOUTCLK or RXRECCLK ports. If you want to constrain TXOUTCLK or RXRECCLK, a PERIOD constraint should be added to the TXOUTCLK or RXRECCLK port of the GTP_DUAL.
AR# 30449
Date Created 03/24/2008
Last Updated 02/27/2013
Status Active
Type General Article