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AR# 30469

10.1 Timing Analyzer/Spartan-3A DSP - Period constraint is not being translated correctly for DCM_SP

Description

UCF : 

NET "clk" TNM_NET = "clk"; 

TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %; 

 

The 9.2iSP4 has translated the constraint into the following PCF line: 

TS_dll_clk2x180 = PERIOD TIMEGRP "dll_clk2x180" TS_clk / 2 PHASE 5 ns HIGH 50%; 

 

But, in 10.1, it has been translated into the following PCF line without PHASE : 

TS_dll_clk2x180 = PERIOD TIMEGRP "dll_clk2x180" TS_clk / 2 HIGH 50%;

Solution

This problem has been fixed in the latest 10.1 Service Pack available at: 

http://www.xilinx.com/support/download/index.htm
The first service pack containing the fix is 10.1 Service Pack 1.

AR# 30469
Date Created 03/24/2008
Last Updated 05/22/2014
Status Archive
Type General Article