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AR# 3050

4.1i SIMPRIMS - Why do the models for the X_RAMD16 have only one output port?


Keywords: Simprim, Verilog, VHDL

Urgency: Standard

General description:
A dual port RAM has two output ports, SPO (single port out) and DPO
(dual port out). Why do the Verilog and VHDL SIMPRIM models for the
Dual Port RAM primitive (X_RAMD16) have only one output port?

For example, in the Verilog SIMPRIM library, the
X_RAMD16 port declaration shows only one output called "OUT":

module X_RAMD16 (OUT, IN, CLK, WE, WADR0, WADR1, WADR2,


The X_RAMD16 in a post-Ngdbuild, post-Map, or post-Par netlist is
only part of the model for a RAM16x1D Unified Library component.

The dual output RAM16X1D component is actually modeled using
a combination of an X_RAMD16 and and an X_RAMS16 SIMPRIM
(single port Synchronous RAM) in the simulation netlist.

The main reason behind this is because the Xilinx Alliance Tools
require that all SIMPRIM (simulation primitive models) have only ONE
output pin. In keeping with this rule, the X_RAMD simprim has only
a DPO (dual port output) pin. (Note, however, that it still has both read
and write address ports.)

To achieve the full function of the RAM16X1D library element, the
X_RAMD simprim is wired in parallel with an X_RAMS (single port sync
RAM) simprim. The X_RAMS simprim is used to generate the SPO
output of the RAM16X1D, using the write address as its address input.
AR# 3050
Date 08/25/2003
Status Archive
Type ??????
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