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AR# 30518

LogiCORE Initiator/Target for PCI-X - 133 MHz embedded designs not using RCLK input


Why is the reference clock (RCLK) input necessary for PCI-X 133 designs?

Is the RCLK input necessary for PCI-X 133 MHz embedded designs?


In the PCI-X v6.7 Core, the internal clock-management structure was modified to use a Digital Clock Manager (DCM) due to PLL timing corrections that caused the previous structure to fail timing. The DCM has two operating modes, Low Frequency Mode and High Frequency Mode, with a crossover of 120 MHz. In the PCI-X Core, the DCM operates in Low Frequency Mode, which has a range of 32-120 MHz. This means that, in a fully compliant PCI-X design, the DCM internal frequency must be halved when the bus is running at 133 MHz. However, this step-down cannot be fixed since the PCI-X bus can run as low as 50 MHz, which when halved would run below the 32 MHz minimum for Low Frequency Mode.

The PCI-X 133 MHz Core in v6.7 uses the Dynamic Reconfiguration Port (DRP) on the DCM to switch the halving circuitry on and off. For reliability, the DRP logic borrows the reference clock RCLK from PCI mode. An embedded design that runs exclusively in PCI-X mode at a fixed frequency does not require this adjustment logic and, consequently, does not require RCLK.

If you have an embedded 66-133 MHz design without RCLK traces on the board, the v6.7 Core will not function as a straight drop-in replacement. The RCLK in the new core will be left unconnected, causing the DCM to hang in perpetual reset. To make a fixed-frequency 66-133 MHz design that does not use RCLK, follow the procedure below:

1. Generate your core as PCI-X 66 MHz. This configuration does not use the DRP logic since it does not run above the 120 MHz ceiling for DCM Low Frequency Mode.

2. Change the timing specifications in the UCF file (under the example_design directory) as needed. In the case of 133 MHz, for example:

NET "PCLK" PERIOD = 7.500 ;


3. If your fixed frequency runs above 120 MHz, set the DCM to High Frequency Mode by modifying pcix_lc_64.v|vhd (under example_design).


Add the attribute to the DCM_BASE instantiation:





Add the generic to both the declaration and instantiation of DCM_BASE:

component DCM_BASE

generic (



port ( ...


port map (CLKIN => CLK_NUB, ...

Revision History

05/07/2008 - Replaced AR 30847 with 30518; 30518 is referenced in release notes.

04/25/2008 - Initial Release

AR# 30518
Date Created 05/07/2008
Last Updated 12/15/2012
Status Active
Type General Article