What is the purpose of the buffer in an SRIO design, and how does it work?
Since the Xilinx SRIO Physical layer and Logical Layer do not have any storage for packets, a buffer design is needed to store data and forward complete packets between the Physical Layer and Logical Layer modules.
A buffer design is provided as a reference design so that you can modify the buffer as required by the application you are running. You must select the Design Example module when generating the core. All the files related to the Design Example are in /example_design sub-directory, and the files related to the buffer design are located in /buffer sub-directory. The files contain comments to clarify how the design works. While you are not required to use the buffer design provided by Xilinx, some type of buffer will be needed, more likely the store and forward type.
The Xilinx buffer design consists of two parts, one for the receive side (rx.v) and one for the transmit side (tx_wrapper.v). The rx.v receives packets from the PHY layer and passes them on in order to the Logical layer. It will reject packets of insufficient priority, based on a system of queue slots that are "reserved" for only certain priority levels or higher. The receive buffer provided with the v4.3 Core is large enough to store eight maximum size packets (256 bytes). With the heavy traffic of large packets, it is possible to fill up the buffer, which can cause disconnects to the link and affect the overall bandwidth of the system. In this case, it is possible to increase the capacity of the buffer. To accomplish this, see (Xilinx Answer 30525). For more information on rx. v, refer to the comments provided in the rx.v file
The buffer for the transmitter side is used for the temporary storage of the packet data before sending it off to the Physical layer. It handles prioritization of the packets, as well. For more information on transmitter buffer, refer to the comments in tx_control.v.