Resolution 1This resolution contains references to IBM's PPC440G5V4 and PowerPC 440 Processor Block Errata, excluding PowerPC 440 APU (see Resolution 2).
- The IBM PPC440G5V4 Errata for all of the Virtex-5 FXT devices is available at:
http://www.xilinx.com/txpatches/pub/documentation/misc/ppc440g5v4_er.pdf1. Branch History Table
Category: 5
The Branch History Table (BHT) must be disabled for deterministic execution latency.
Resolution 2 This resolution contains a list of Answer Records related to PowerPC 440 APU Errata.
APU #1. For FPU/APU operation, CCR0[9] should be set to 1. Although this bit is marked as "Reserved" in the IBM PPC440x5 User Guide, it must be set for FPU operation.
APU #2. After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of events, the Auxiliary Processor Unit (APU) can lock up or corrupt the data.
Refer to
(Xilinx Answer 30570) for additional details and work-arounds.
APU #3. When the floating-point execution is disabled in the PowerPC 440 processor but enabled in the APU controller and an FPU instruction is executed, the processor can generate a spurious program exception, instead of an FPU-unavailable exception.
Refer to
(Xilinx Answer 30579) for additional details and work-arounds.
Resolution 3:This resolution contains a list of Answer Records related to "apu_fpu_virtex5_v1_00_a" in EDK 10.1 Service Pack 2.
FPU # 1, Enabling FPU Exceptions could cause Data Corruption.
Please refer to
(Xilinx Answer 31179) for additional details and work-arounds.
FPU # 2, apu_fpu_virtex5_v1_00_a, XST synthesis errors out when C_USE_RLOCS=1.
Please refer to
(Xilinx Answer 31181) for additional details and work-arounds.