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AR# 30529

PowerPC 440 processor - Master Answer Record for all Virtex-5 FXT devices, including errata and work-around information

Description

Keywords: PPC440, APU, UDI, PPC, PVR, FCM, FPU, Xbar, MIB, PLBV46, MPLB, SPLB, PPC 440, apu_fpu, apu_fpu_virtex5_v1_00_a


This Master Answer Record is a single document for all PowerPC 440 processor-related items, and contains the following information:

- References to IBM's PPC440G5V4 and PowerPC 440 Processor Block Errata, excluding PowerPC 440 APU Errata (see Resolution 2 for details)
- PowerPC 440 APU Errata
- PPC440 usage in EDK and ISE 10.1

This Answer Record also provides an overview of these errata, which are classified according to system impact and work-around availability.

Category 1:
Major impact, no work-around is available. A problem has a major impact if it results in a system crash, a hard failure, an unrecoverable soft failure, significant performance degradation, or the storage of incorrect data.

Category 2:
Major impact, a work-around is impractical to implement, or a substantial risk of encountering the same or additional problems (including performance issues) exists after the work-around is implemented.

Category 3:
Major impact, a work-around is available. Application of the work-around either eliminates the problem or reduces it to a minor impact issue.

Category 4:
Minor impact, no work-around is available. Minor impact problems result in slight to moderate performance degradation, or are a functional variance from the specification.

Category 5:
Minor impact, a work-around is available. Minor impact problems result in slight to moderate performance degradation, or are a functional variance from the specification.

Category 6:
Design enhancement.

Solution

Resolution 1

This resolution contains references to IBM's PPC440G5V4 and PowerPC 440 Processor Block Errata, excluding PowerPC 440 APU (see Resolution 2).

- The IBM PPC440G5V4 Errata for all of the Virtex-5 FXT devices is available at:
http://www.xilinx.com/txpatches/pub/documentation/misc/ppc440g5v4_er.pdf

1. Branch History Table
Category: 5
The Branch History Table (BHT) must be disabled for deterministic execution latency.

Resolution 2

This resolution contains a list of Answer Records related to PowerPC 440 APU Errata.

APU #1. For FPU/APU operation, CCR0[9] should be set to 1. Although this bit is marked as "Reserved" in the IBM PPC440x5 User Guide, it must be set for FPU operation.

APU #2. After a Translation Look-aside Buffer (TLB) miss caused by an instruction fetch, in a very specific combination of events, the Auxiliary Processor Unit (APU) can lock up or corrupt the data.
Refer to (Xilinx Answer 30570) for additional details and work-arounds.

APU #3. When the floating-point execution is disabled in the PowerPC 440 processor but enabled in the APU controller and an FPU instruction is executed, the processor can generate a spurious program exception, instead of an FPU-unavailable exception.
Refer to (Xilinx Answer 30579) for additional details and work-arounds.

Resolution 3:

This resolution contains a list of Answer Records related to "apu_fpu_virtex5_v1_00_a" in EDK 10.1 Service Pack 2.

FPU # 1, Enabling FPU Exceptions could cause Data Corruption.
Please refer to (Xilinx Answer 31179) for additional details and work-arounds.

FPU # 2, apu_fpu_virtex5_v1_00_a, XST synthesis errors out when C_USE_RLOCS=1.
Please refer to (Xilinx Answer 31181) for additional details and work-arounds.
AR# 30529
Date Created 03/20/2008
Last Updated 06/24/2008
Status Active
Type General Article