Solution

Issues Addressed in 10.1 ISE Service Packs



Architecture Wizard

(SP3) - (Xilinx Answer 20317) 10.1 CORE Generator - The clocking wizard for the Automotive Spartan-3A DSP devices is not selectable



Configuration

(SP1) - (Xilinx Answer 30102) 9.2i iMPACT - Spartan-3A DSP Starter Kit board, indirect BPI operations error

(SP1) - (Xilinx Answer 30450) 10.1 iMPACT - When generating an SVF for an XCFxxP PROM, following message occurs: "The operation did not complete successfully"

(SP1) - (Xilinx Answer 30127) 9.2i - iMPACT - Error results when using the "Automatically Generate PROM or ACE File" option in ISE

(SP1) - (Xilinx Answer 30128) 10.1 iMPACT - "ERROR:Bitstream:99" occurs when running "Generate Target PROM/ACE File" from ISE

(SP1) - (Xilinx Answer 30212) Spartan-3AN - Known issues with In-System Programming (ISP) of the Spartan-3AN via SVF files

(SP2) - (Xilinx Answer 30184) 10.1 iMPACT - "WARNING:iMPACT:923 - Cannot find cable, check cable setup"

(SP2) - (Xilinx Answer 30445) 10.1 iMPACT - There is no option to program my Platform Flash as Configuration Master

(SP2) - (Xilinx Answer 30382) Platform Cable USB Install - System exhibits kernel panic when installing cable drivers on Linux

(SP2) - (Xilinx Answer 30476) 10.1 iMPACT - Readback file is incorrect for CoolRunner-II

(SP2) - (Xilinx Answer 30914) 10.1 iMPACT - "ERROR:iMPACT:2855 - Add Device failed."

(SP2) - (Xilinx Answer 30918) 10.1 iMPACT - Tool reports that "Blank Check" has passed but there is Data in the SPI device

(SP2) - (Xilinx Answer 30843) 10.1 iMPACT - I see "FATAL_ERROR:GuiUtilities:Gq_Application.c:590:1.20" when attempting to generate an XSVF File

(SP3) - (Xilinx Answer 30399) 10.1 iMPACT - The message "Readback to file failed" appears when I attempt to readback an XC9572xl CPLD

(SP3) - (Xilinx Answer 31204) 10.1 iMPACT - When I assign a <file_name>.RBT or <file_name>.bit file to my Spartan-3A device I cannot choose programming properties In SVF mode

(SP3) - (Xilinx Answer 30983) 10.1 ChipScope Pro - When I use CseJTAG and the CseJtag_shiftDeviceDR, the last bit shifted out is always 0

(SP3) - (Xilinx Answer 31097) 10.1 iMPACT - Concurrent mode is ON by default in the GUI and can not be disabled

(SP3) - (Xilinx Answer 31206) 10.1 iMPACT - When I update an existing MCS file for direct SPI config, impact does not load the new file

(SP3) - (Xilinx Answer 31628) 10.1 iMPACT - When I create an SVF a .isc file to program a CoolRunner-II device, I receive "ERROR:iMPACT - Failed ScanDR: TDO does not match Expected TDO" when I play it

(SP3) - (Xilinx Answer 31281) 10.1 BitGen, Spartan-3A/N/DSP - 1532 programming file (.isc) is generated incorrectly

(SP3) - (Xilinx Answer 30956) Virtex-4 Configuration - The IEEE 1532 programming flow is not programming the device



Timing & Constraints

(SP1) - (Xilinx Answer 30367) 10.1 Constraints Editor - DDR OFFSET IN/OUT Wizard uses FALLING keyword for both rising and falling edge elements, and the pad timegrp name includes extra letters

(SP1) - (Xilinx Answer 30469) 10.1 Timing Analyzer/Spartan-3A DSP - Period constraint is not being translated correctly for DCM_SP

(SP1) - (Xilinx Answer 30461) 10.1 Constraint Editor- Creating a register group in "ClK to Pad" or "Pad to Setup" generates an incorrect syntax

(SP1) - (Xilinx Answer 30335) 10.1 Timing Analyzer/ Constraints Editor/Floorplan Editor/PACE - Launching via command line causes multiple issues (crashes to incorrect files)

(SP1) - (Xilinx Answer 29999) 10.1 Constraints Editor - New Input/Output Wizard dialog does not show Pad timegroup

(SP1) - (Xilinx Answer 30370) 10.1 Constraints Editor - OFFSET IN (Clock to Setup) Wizard does not provide "ns" as valid values

(SP1) - (Xilinx Answer 30365) 10.1 Timing Analysis - False Hold violation in FROM:TO/OFFSET IN constraint

(SP1) - (Xilinx Answer 30358) 10.1 Timing Constraints - OFFSET OUT without a requirement causes "ERROR:Pack:1653"

(SP1) - (Xilinx Answer 30837) 10.1 Timing Constraint - New OFFSET IN Rising/Falling keywords ignore DCM phase in analysis

(SP1) - (Xilinx Answer 30838) 10.1 Constraint Editor - OFFSET OUT constraints are not created

(SP1) - (Xilinx Answer 30839) 10.1 Constraint Editor - Switching UCF does not always re-load editor content correctly

(SP1) - (Xilinx Answer 30840) 10.1 Timing Analyzer - Does not report failing paths for setup error

(SP2) - (Xilinx Answer 31105) 10.1 Constraints System - TNM Constraint applied incorrectly

(SP2) - (Xilinx Answer 29998) 10.1 Constraints Editor - Pad group is incorrectly listed under "Input Register Group"

(SP2) - (Xilinx Answer 31090) 10.1 Constraint Editor- Constraints are not written to UCF file

(SP2) - (Xilinx Answer 31091) 10.1 Constraint Editor - Cannot save constraints after modifying certain existing miscellaneous constraints

(SP2) - (Xilinx Answer 31102) 10.1 Constraints Editor - Crashes when "TIMESPEC Name" and "Reference TIMESPEC Name" is kept same under "Slow/Fast Exceptions" tab

(SP2) - (Xilinx Answer 31104) 10.1 Constraints Editor - Not able to create NET OFFSET constraint using Constraints Editor

(SP2) - (Xilinx Answer 31123) 10.1 Constraints Editor - User notified twice to use Project Navigator to update project

(SP2) - (Xilinx Answer 30622) 10.1 Timing Analysis - Using REFERENCE PIN keyword with the OFFSET OUT constraint does not report the bus skew in the data sheet section

(SP2) - (Xilinx Answer 30623) 10.1 Timing Analyzer - The bus skew reporting for the OFFSET OUT constraint in the presence of the REFERENCE_PIN keyword is incorrect

(SP2) - (Xilinx Answer 30624) 10.1 Timing Analyzer - Negative slack value on OFFSET OUT constraint results in "Invalid Slack Equation" dialog

(SP2) - (Xilinx Answer 30650) 10.1i Timing Analyzer - "FATAL_ERROR:TimingToolsC:Port_Main.h:143:1.13.2.3 - This application has discovered an exceptional condition"

(SP2) - (Xilinx Answer 31092) 10.1 Timing Analyzer - It crashes with reporting the segmentation fault error

(SP2) - (Xilinx Answer 31093) 10.1 Timing Analyzer - GTX clocks TXOUTCLK0 and TXOUTCLK1 are not analyzed correctly

(SP2) - (Xilinx Answer 31094) 10.1 Timing Analyzer - "FATAL_ERROR:Timing:bastwgraphedit.c:2262:1.36.2.4 with multiple FROM:TOs"

(SP2) - (Xilinx Answer 31113) 10.1 Timing Analyzer - I cannot crossprobe from Timing Analyzer to Floorplan Implemented (FPI) or to Schematic viewer for several new parts

(SP2) - (Xilinx Answer 31114) 10.1 Timing Analyzer - Context menu crossprobe links for Floorplan Implemented (FPI) and Translated netlisd view are grayed out

(SP2) - (Xilinx Answer 31106) 10.1 Timing Analyzer - Opening an old project with TA invokes multiple messages to use Project navigator to update project

(SP2) - (Xilinx Answer 31124) 10.1 Timing Analyzer - Standalone version launches when TWX file is not specified

(SP3) - (Xilinx Answer 31527) 10.1 Constraints Editor - Group by element type is not listing "HSIOs", "CPUs", "MULTs", "DSPs", and "OTHERs" as options

(SP3) - (Xilinx Answer 31525) 10.1 Constraints Editor - Crashes when attempting to delete Slow/Fast Exceptions constraints

(SP3) - (Xilinx Answer 31526) 10.1 Constraints Editor - Output IO (Clock to Pad) Wizard will not allow the use of the OK button

(SP3) - (Xilinx Answer 31524) 10.1 Constraints Editor - Fatal error occurs when attempting to enter a voltage

(SP3) - (Xilinx Answer 31109) 10.1 Incremental Design/Timing - Timing constraint change causes Partitions to be reimplemented

(SP3) - (Xilinx Answer 30464) 10.1i Timing Analyzer - The Path Tracing tab does not show reg_sr_r or reg_sr_o for this design

(SP3) - (Xilinx Answer 30369) 10.1 Constraint System - Lack of error numbers and UCF line numbers for constraint syntax issues

(SP3) - (Xilinx Answer 30460) 10.1i Timing Analyzer/Floorplan Editor - Cross-probing with non-updated NCD shows incorrect path

(SP3) - (Xilinx Answer 31522) 10.1 TRCE, Timing Analyzer - Tbxcy value in Spartan-3E is overreported

(SP3) - (Xilinx Answer 31530) 10.1 Timing Analyzer - Links are not working in "Table of Timegroups" section of timing reports

(SP3) - (Xilinx Answer 31124) 10.1 Timing Analyzer - Standalone version launches when TWX file is not specified

(SP3) - (Xilinx Answer 31529) 10.1 TRCE - MAP issues errors stating that timing cannot be met due to component delays

(SP3) - (Xilinx Answer 31276) 10.1.02 Timing Analyzer - Incorrect clock skew reported

(SP3) - (Xilinx Answer 30335) 10.1 Timing Analyzer/ Constraints Editor/Floorplan Editor/PACE - Launching via command line causes multiple issues (crashes to incorrect files)



Coregen

(SP1) - (Xilinx Answer 30856) 10.1 CORE Generator - ChipScope core is not created if EDIF is selected as netlist output type

(SP1) - (Xilinx Answer 30528) 10.1 CORE Generator - CIC and FIR Filter graphs do not display properly on Windows NT64, Vista64

(SP1) - (Xilinx Answer 30613) 10.1 CORE Generator - ERROR:sim - CreateVHDLStructuralModel : Could not read S:/coregen/tmp/_cg/srio_v4_1/rio_log_io_v4_1.ngc

(SP1) - (Xilinx Answer 30515) 10.1 CORE Generator - White space in project directory causes "ERROR:coreutil - Failure to generate output products"

(SP1) - (Xilinx Answer 30196) 10.1 CORE Generator - ?ERROR:sim - NgdBuild:15 - Missing "-p" option and no target architecture available!"

(SP2) - (Xilinx Answer 30515) 10.1 CORE Generator - White space in project directory causes "ERROR:coreutil - Failure to generate output products"

(SP3) - (Xilinx Answer 31640) 10.1 CORE Generator - COE files for CAM core do not currently support "X" or "U" characters

(SP3) - (Xilinx Answer 31428) 10.1 ChipScope Pro - "ERROR: sim - DoQuickCopy : Could not execute xlicmgr.exe"



Floorplan Editor

(SP1) - (Xilinx Answer 30278) 10.1 Floorplanner - S3AN200 FT256 pin locations shown incorrectly in Floorplan View

(SP1) - (Xilinx Answer 29989) 10.1 Floorplan Editor - IOB Attributes are always written to the top.ucf

(SP1) - (Xilinx Answer 30375) 10.1 Floorplan Editor - When opening Floorplan Editor, an error occurs: "FATAL_ERROR:GuiUtilities:Gq_Application.c:590:1.20 .."

(SP1) - (Xilinx Answer 30368) 10.1 Project Navigator - Creating a new I/O pin assignment with the New Source Wizard causes a crash

(SP1) - (Xilinx Answer 30366) 10.1 Floorplan Editor - Unable to see all Vref pins and right side I/O pins for Spartan-3, Spartan-3A, Spartan-3AN, and Spartan-3A DSP devices

(SP1) - (Xilinx Answer 30360) 10.1 Floorplanner - Crashes when the cursor is placed over an assigned pin

(SP1) - (Xilinx Answer 30359) 10.1 Floorplanner/ Automotive Spartan-3A - Unable to view placed block RAM

(SP1) - (Xilinx Answer 30540) 10.1 Floorplan Editor - Open FloorPlan IO - Pre-Synthesis will make ISE hang

(SP2) - (Xilinx Answer 31111) 10.1 Floorplan Editor - When an existing area group range is adjusted, the associated partition does not go out of date

(SP3) - (Xilinx Answer 30371) 10.1 Floorplan Editor - Area Group ranges are incorrectly written

(SP3) - (Xilinx Answer 31076) 10.1 Floorplan Editor - PACE opens instead of the integrated Floorplanner for Automotive Spartan-3A DSP designs when launching any "Floorplan" process

(SP3) - (Xilinx Answer 31531) 10.1 Floorplan Editor - Dragging and dropping a level of hierarchy is generating incorrect constraints

(SP3) - (Xilinx Answer 30361) 10.1 Floorplan Editor - Unable to change the IOStandard



Implementation

(SP1) - (Xilinx Answer 30472) 10.1 ChipScope Pro - Creating PlanAhead project when source files contain ChipScope cores results in "FATAL_ERROR:Portability:basutformat.c:146:1.19"

(SP1) - (Xilinx Answer 30126) 9.2.04i PAR - For Virtex-5 PLL to DCM Core, PAR fails to place the PLL and DCM in the same CMT block

(SP1) - (Xilinx Answer 30091) 9.2i MAP - SmartGuide: "FATAL_ERROR:Pack:pksbashapemerge.c:259:1.26.34.1"

(SP1) - (Xilinx Answer 30035) 9.2i SP4 Virtex-5 - OBUFTDS Slave IOB has incorrect connectivity on tristate enable

(SP1) - (Xilinx Answer 30283) 10.1 ChipScope Pro/ISE - "ERROR:LIT:266/267/296/407/409/456" or "ERROR:Maplib" occurs during implementation if ChipScope cores are present

(SP3) - (Xilinx Answer 31624) 10.1 MAP - A feedback path involving a MUX is improperly trimmed

(SP3) - (Xilinx Answer 31625) 10.1 Virtex-5 MAP - Crash during "Mapping design into LUTs..."

(SP3) - (Xilinx Answer 30283) 10.1 ChipScope Pro/ISE - "ERROR:LIT:266/267/296/407/409/456" or "ERROR:Maplib" occurs during implementation if ChipScope cores are present

(SP3) - (Xilinx Answer 31623) 10.1 Virtex-5 PLACE - Long carry chains taller than device or area group range are not aligned

(SP3) - (Xilinx Answer 31603) 10.1 Virtex-5 MAP - "INTERNAL_ERROR:Pack:pktbaplacepacker.c:897:1.139.4.6 - Unable to obey placement request which requires the combination ..."

(SP3) - (Xilinx Answer 31150) 10.1 Virtex-4 PLACE - Routing congestion due to poor Clock Region allocation

(SP3) - (Xilinx Answer 31503) 10.1 Virtex-5 PAR - "ERROR:Route:472 - This design is unrouteable"

(SP3) - (Xilinx Answer 31502) 10.1 Virtex-4 PLACE - "INTERNAL_ERROR:Place:basplbscore.c:507:1.46 - attempting to provisionally place multiplecomps in the same site"



Project Navigator

(SP1) - (Xilinx Answer 30375) 10.1 ISE - When opening PlanAhead, an error occurs: "FATAL_ERROR:GuiUtilities:Gq_Application.c:590:1.20 .."

(SP1) - (Xilinx Answer 30376) 10.1 ISE - Generate Tcl script on Spartan-3A design error: "ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'can't read "aMktToDevNameInfo(Spartan3A and Spartan3AN)": no such element in array'"

(SP1) - (Xilinx Answer 30611) 10.1 ISE - Project -> Apply Project Properties fails with "ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'Could not create the Tcl Wrapper component for IInterface'"

(SP1) - (Xilinx Answer 30852) 10.1 ISE - Translate error: "ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result invalid command name "0""

(SP1) - (Xilinx Answer 30861) 10.1 ISE - Project Navigator New Project Wizard freezes if the Finish button is selected twice

(SP1) - (Xilinx Answer 30862) 10.1 ISE - Project Navigator freezes if I select File -> Open and select an NGC or NGR file

(SP1) - (Xilinx Answer 30863) 10.1 ISE - Synthesis fails on design with an XMP source, however, the Synthesis process receives a green check mark

(SP1) - (Xilinx Answer 30864) 10.1 ISE - Deleted or changed design constraints are still being used by implementation

(SP1) - (Xilinx Answer 30865) 10.1 ISE - System Generator Module cannot be set as top module in Project Navigator

(SP1) - (Xilinx Answer 30866) 10.1 ISE - Failing Synplify synthesis is shown in Project processes with completed successfully status

(SP1) - (Xilinx Answer 30867) 10.1 ISE - Open snapshot fails for design containing partitions

(SP1) - (Xilinx Answer 30868) 10.1 ISE - Running the .restore script to recreate a project does not restore a System Generator source to the project

(SP1) - (Xilinx Answer 30870) 10.1 ISE - Running SmartGuide and MPPR error: "ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'error copying "mppr_result.par" ..."

(SP1) - (Xilinx Answer 31080) 10.1 ISE - Project Navigator gives segmentation Fault on startup when run over x-server

(SP2) - (Xilinx Answer 30655) 10.1 ISE - Saving Generate Tcl script to remote location results in bad name and path

(SP2) - (Xilinx Answer 30667) 10.1 ISE - Migrating an EDIF project from ISE 8.x to ISE 10.1 fails

(SP2) - (Xilinx Answer 30795) 10.1 ISE - My EDK project is not recognized inside my ISE project; "WARNING: there is no XPS project associated with this design"

(SP2) - (Xilinx Answer 31205) 10.1 ISE - Stopping a process in Project Navigator does not terminate the underlying application

(SP2) - (Xilinx Answer 31213) 10.1 ISE - Project Navigator process window does not reflect error status for ERROR:Route:472

(SP2) - (Xilinx Answer 31214) 10.1 ISE - Project Navigator asks me to migrate a project that was created using the same version

(SP2) - (Xilinx Answer 31215) 10.1 ISE - Project Navigator closes unexpectedly when saving top level source file with invalid component instantiation

(SP2) - (Xilinx Answer 31217) 10.1 ISE - Migrating an ISE 8.x project to ISE 10.1 on Linux causes a segmentation fault

(SP2) - (Xilinx Answer 31218) 10.1 ISE - Adding an EDIF (.edn) file with partitions causes Project Navigator to fail

(SP2) - (Xilinx Answer 31219) 10.1 ISE - Project Navigator fails to process design containing System Generator module on Window Vista

(SP2) - (Xilinx Answer 31220) 10.1 ISE - Running create_partitions or create_libraries procedures from a Generated Tcl Script closes the project

(SP2) - (Xilinx Answer 31224) 10.1 ISE - Project Navigator: Project -> Generate Tcl Script process fails if spaces are in the specified file name

(SP2) - (Xilinx Answer 31225) 10.1 ISE - Sourcing a Project Navigator Generated Tcl script returns: can't read "myScript": no such variable

(SP2) - (Xilinx Answer 31226) 10.1 ISE - Project Navigator "Generate IBIS Model" process does not run

(SP3) - (Xilinx Answer 31642) 10.1 ISE - Generate Programming File Process causes Bitgen to fail with ERROR:Portability:90 - Command line error:

(SP3) - (Xilinx Answer 30562) 10.1 ISE - Opening a 9.2i project gives: "ERROR:ProjectMgmt:387 - TOE: ITclInterp::ExecuteCmd gave Tcl result 'list element in quotes ...'"

(SP3) - (Xilinx Answer 31168) 10.1 ISE - View HDL instantiation Template results in "ERROR:HDLParsers:3264 - Can't read file "<DCM module>.v(hd)" "

(SP3) - (Xilinx Answer 31218) 10.1 ISE - Adding an EDIF (.edn) file with partitions causes Project Navigator to fail

(SP3) - (Xilinx Answer 30861) 10.1 ISE - Project Navigator New Project Wizard freezes if the Finish button is selected twice

(SP3) - (Xilinx Answer 31304) 10.1 ISE - Project Navigator sends incorrect top level module to synthesis for schematic design

(SP3) - (Xilinx Answer 30663) 10.1 ISE - The Project Navigator Cleanup Project File process incorrectly deletes NGC and EDN source files

(SP3) - (Xilinx Answer 25234) 10.1 ISE - The Project Navigator Create Schematic Symbol process fails for ABEL files

(SP3) - (Xilinx Answer 31600) 10.1 Schematic Editor - "Error : Symbol Not Found" when using User Libraries

(SP3) - (Xilinx Answer 31644) 10.1 ISE Text Editor - Setting breakpoints for ISIM causes an error

(SP3) - (Xilinx Answer 30039) 10.1 ISE - Project Navigator does not handle the same file name in different HDL libraries

(SP3) - (Xilinx Answer 31641) 10.1 ISE - Pin Assignment and Floorplanning for the Virtex-5 TXT devices only supported using the Xilinx PlanAhead tool

(SP3) - (Xilinx Answer 23536) 10.1 ISE - Project Navigator allows one State Diagram (.dia) file to be added to a project

(SP3) - (Xilinx Answer 31637) 10.1 ISE - Synthesizing a design with an XMP submodule in Synplify Pro results in "Error: Reference to undefined module "system"

(SP3) - (Xilinx Answer 31643) 10.1 Schematic - Schematic Editor hangs when renaming a port with invalid name.



Schematic

(SP1) - (Xilinx Answer 30680) 10.1 Schematic - Editing a preference for a schematic, symbol editor, or RTL/Technology viewer results in a crash if the application is in use

(SP2) - (Xilinx Answer 31228) 10.1 Schematic - Copy/Paste operations require two key strokes when using keyboard shortcuts



Simulation

(SP1) - (Xilinx Answer 30332) 10.1 ISim ( ISE Simulator) - "FATAL_ERROR:Simulator:Fuse.cpp:419:$Id: Fuse.cpp.v"

(SP2) - (Xilinx Answer 30626) IP-DSP - Why are there mismatches between the behavioral simulation and the post-translate simulation when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine CoSine LUT IP?

(SP2) - (Xilinx Answer 31065) 10.1.01 System Generator for DSP - Why do I receive "ERROR:Simulator:798 - Unknown signal 1073807366 received" and "Warning:HDLCompiler:746 - "N:/K.31/rtf/vhdl/src/ieee/numeric_std.vhd" Range is empty" when simulating an IP core in System Generator 10.1?

(SP2) - (Xilinx Answer 31079) 10.1Sp1 ISim - "ERROR:Simulator:798 - Unknown signal 1073807366 received"

(SP2) - (Xilinx Answer 31125) ModelSim (SE/PE) 6.3c - (Vopt -3473) Component instance "gtx_dual_swift_bw_i:gtx_dual_swift" is not bound

(SP2) - (Xilinx Answer 30815) 10.1 SimPrim, Timing Simulation - Post PAR simulation does not work as expected

(SP3) - (Xilinx Answer 31167) 10.1 ISim - ISim compiler exits without any error message

(SP3) - (Xilinx Answer 30913) 10.1: ISim: ERROR: Signal EXCEPTION_ACCESS_VIOLATION received



Speeds File

(SP2) - (Xilinx Answer 23788) Virtex-5 - Speeds File Revision History

(SP2) - (Xilinx Answer 29393) Spartan-3A DSP - Speeds File Revision History

(SP2) - (Xilinx Answer 24981) Spartan-3A/3AN - Speeds File Revision History

(SP2) - (Xilinx Answer 12201) Speeds Files - What speeds files are currently installed for Virtex/-E/-II/-II Pro/-4/-5 and Spartan-II/-IIE/-3 device families in ISE?



XST

(SP1) - (Xilinx Answer 24941) 9.2i ChipScope Serial I/O Toolkit - "ERROR:Xst:917 - Undeclared signal <C_NUM_OF_CHANNEL>"





Issues Addressed in other 10.1 Service Packs



EDK

(SP2) - (Xilinx Answer 30704) 10.1 Install - EDK Service Pack Release Notes (README)



DSP

(SP1) - (Xilinx Answer 30802) 10.1.01 System Generator for DSP - Release Notes/README and Known Issues List

(SP2) - (Xilinx Answer 31216) 10.1.01 System Generator for DSP - Release Notes/README and Known Issues List

(SP2) - (Xilinx Answer 31248) AccelDSP Synthesis Tool - Release Notes/README and Known Issues List



ChipScope Pro

(SP2) - (Xilinx Answer 30801) 10.1 ChipScope Pro Install - Service Pack Release Notes (README)