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AR# 30541

10.1 EDK - PowerPC 440 processor usage in EDK and ISE 10.1 and latest Memory Controller data sheet and patch

Description

This Answer Record contains two resolutions: 

 

Resolution 1 relates to the latest Memory Controller data sheet and the patch for "ppc440mc_ddr2_v1_00_a" and "ppc440mc_ddr2_v1_01_a" cores. 

 

Resolution 2 relates to PowerPC 440 processor usage in EDK and ISE 10.1, including the latest version of the "Embedded Processor Block in Virtex-5 FXT FPGAs Reference Guide" (ug200.pdf).

Solution

Resolution 1 

 

10.1 EDK and 10.1 EDK SP1- for the latest patch for "ppc440mc_ddr2_v1_00_a" and "ppc440mc_ddr2_v1_01_a" cores, see (Xilinx Answer 30835)

 

The latest version of the Memory Controller data sheet is located at: 

http://www.xilinx.com/txpatches/pub/documentation/misc/ppc440mc_ddr2.pdf
 

This data sheet and the latest patch will be delivered in Service Pack 2. 

 

Resolution 2 

 

The following relates to the document titled "Embedded Processor Block in Virtex-5 FXT FPGAs Reference Guide" version 1.0, bundled with EDK and ISE 10.1. 

 

The documentation for the PowerPC 440 processor shipped with 10.1 (embedproc_ug200.pdf) has DCR 0x54, bit 23 set. This bit is reserved and must be set to "0". The latest version of the "Embedded Processor Block in Virtex-5 FXT FPGAs Reference Guide" (ug200.pdf) is located at: 

http://www.xilinx.com/support/documentation/user_guides/ug200.pdf
 

The following relates to the PowerPC 440 processor wrapper IP in EDK: 

 

If your PowerPC design uses the crossbar interrupt request signal (PPCEICINTERCONNECTIRQ output), the parameter C_MPLB_WDOG_ENABLE must be set to 0. This applies to ppc440_virtex5_v1_00_a. The parameters C_MPLB_WDOG_ENABLE and C_MPLB_COUNTER will not be supported in subsequent versions of the ppc440_virtex5.

AR# 30541
Date Created 03/12/2008
Last Updated 05/22/2014
Status Archive
Type General Article