We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30569

10.1 PACE - I cannot find the nets if the design entry is schematic


If the design entry is schematic, I click on I/O Pins "Design Browser"; wrong pin names are displayed, and if I select-drag-release any of them on the "Device Architecture" window and Save, the UCF file created makes NGDBuild fail: 


Annotating constraints to design from file "uuu.ucf" ... 

ERROR:NgdBuild:755 - Line 6 in 'uuu.ucf': Could not find net(s) 'A0' in the 

design. To suppress this error specify the correct net name or remove the 

constraint. The 'Ignore I\O constraints on Invalid Object Names' property 

can also be set ( -aul switch for command line users).


This is a known issue and will be fixed in the future. 


To work around the problem, input constraints in ucf.

AR# 30569
Date Created 03/24/2008
Last Updated 05/22/2014
Status Archive
Type General Article