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AR# 30574

Embedded Tri-mode Ethernet MAC Wrapper (Virtex-4) - Loopback may fail in 1000BASE-X or SGMII mode


When using SGMII or 1000BASE-X loopback, the Virtex-4 Embedded Tri-mode Ethernet MAC Wrappers v4.x and earlier use the GT11 in parallel loopback. The current configuration of the GT11 could cause parallel loopback to fail.


In 1000BASE-X or SGMII mode when loopback is set either through either the configuration vector or via Control Register 0.14, the TEMAC block drives EMAC#PHYLOOPBACKMSB high. When this is high, the TEMAC wrapper files drive "01" into the LOOPBACK#[1:0] port of the GT11 enabling parallel PCS loopback. In the wrapper files EMAC#PHYLOOPBACKMSB is tied to LOOPBACK#[0] and LOOPBACK#[1] is tied to "0."

The GT11 users guide UG076 states that parallel PCS loopback requires the following key constraints:

1) RXCLK0_FORCE_PMACLK must be set to FALSE; otherwise, the PMA clock region can be driven only by the recovered clock.
2) Internal dividers cannot be used because each divider could independently introduce a phase shift, resulting in a phase mismatch between the PCS RXCLK and PCS TXCLK domains.

The current wrapper files both set RXCLK0_FORCE_PMACLK to TRUE (to use rxrecover clock) and uses the internal RX/TX_CLOCK_DIVIDERs. This could cause the PCS parallel loopback to fail.

Possible workarounds:

1) The wrappers can be changed from using parallel loopback to serial loopback. To enable Serial Loopback, when loopback is enabled the loopback input that is fed to the GT11 through the calibration block must be changed from "01" to "11" in the <core_name>_block.v/vhd file.

For VHDL in <core_name>_block.vhd change:

loopback_1_sig <= '0' & loopback_1_i;
loopback_0_sig <= '0' & loopback_0_i;
loopback_1_sig <= loopback_1_i & loopback_1_i;
loopback_0_sig <= loopback_0_i & loopback_0_i;

For Verilog in <core_name>_block.v change:

.LOOPBACK_1 ({1'b0, loopback_1_i }),
.LOOPBACK_0 ({1'b0, loopback_0_i }),
.LOOPBACK_1 ({loopback_1_i , loopback_1_i }),
.LOOPBACK_0 ({loopback_0_i, loopback_0_i }),

When in serial loopback, TXPOST_TAP_PD must also be set to "0." For more information,see UG076.

2) If Parallel Loopback is wanted, to insure that it will always work:

a) A DCM can be added to create rx/txuserclk instead of using the internal clock dividers.
b) RXCLK0_FORCE_PMACLK must be set to FALSE. This can be done either with an attribute change if Loopback will always be enabled, or via the DRP port if loopback needs to be enabled and disabled.
AR# 30574
Date Created 03/19/2008
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-4 Embedded Tri-Mode Ethernet MAC