10.1 Timing Analyzer - RISING/FALLING keywords used to create timegroups are not working
Description
Keywords: Trce, DDR, analysis, 41, 51
When I create timegroups using the RISING/FALLING keywords, I obtain no elements in that group. The following is the UCF syntax:
TIMEGRP "RXCLK1_RISING" = RISING "src_ddr_RxClock_1";
TIMEGRP "RXCLK1_FALLING" = FALLING "src_ddr_RxClock_1";
OFFSET = IN 2.5 ns VALID 5 ns BEFORE "src_ddr_RxClock_1" TIMEGRP "RXCLK1_RISING";
OFFSET = IN 2.5 ns VALID 5 ns BEFORE "src_ddr_RxClock_1" TIMEGRP "RXCLK1_FALLING";
Map reported the following warning messages:
WARNING:MapLib:41 - All members of TNM group "RXCLK3_RISING" have been optimized out of the design.
WARNING:MapLib:41 - All members of TNM group "RXCLK3_FALLING" have been optimized out of the design.
WARNING:MapLib:51 - The offset specification "OFFSET=IN 0 pS VALID 5000 pS BEFORE src_ddr_RxClock_3 TIMEGRP RXCLK3_RISING" has been discarded because its register group (RXCLK3_RISING) was optimized away.
WARNING:MapLib:51 - The offset specification "OFFSET=IN 0 pS VALID 5000 pS BEFORE src_ddr_RxClock_3 TIMEGRP RXCLK3_FALLING" has been discarded because its register group (RXCLK3_FALLING) was optimized away.
Solution
When a DCM/PLL/DLL/BUFR or other clock modifying block is in the clock path, Xilinx recommends using clock-based time groups driven by a clock-modifying block as the base time group instead of the clock time group that drives the clock-modifying blocks.Example:
#Net clkA drives into the DCM
NET clkA TNM = clka_grp;
#BAD constraints
TIMEGRP rising_clka = RISING clka_grp;
TIMEGRP falling_clka = FALLING clka_grp;
#Net clkB is driven from the DCM
NET clkB TNM = clkb_grp;
#GOOD constraints
TIMEGRP rising_clkb = RISING clkb_grp;
TIMEGRP falling_clkb = FALLING clkb_grp;