We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30600

9.2i Virtex-5 MAP - INIT values on BRAM get assigned to zero when packed in the same component as a FIFO


Keyword: RAM18, RAMB36, FIFO

The INIT values of my RAM18 are all set to zero when it is packed together with a FIFO in a RAMB36 Component.

When I lock the memories to separate locations, the INIT values of the BRAM get assigned correctly. Why does this occur?


This is a Map packing bug where the INIT values of a BRAM get corrupted when packed in the same RAM component as the FIFO. This issue will be fixed in ISE version 10.1 SP2.

Meanwhile, the problem can be avoided by locking the BRAM and FIFO instances to different sites, or by using any packing constraint that prevents the BRAM and FIFO from being packed together.

AR# 30600
Date Created 03/25/2008
Last Updated 12/15/2012
Status Active
Type General Article