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AR# 30630

LogiCORE 3GPP LTE Turbo Decoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE 3GPP LTE Turbo Decoder Core.

The following information is listed for each version of the core:

- New Features

- Bug Fixes

- Known Issues

Solution

General LogiCORE 3GPP LTE Turbo Decoder Issues

LogiCORE 3GPP LTE Turbo Decoder v2.0

Initial Release in ISE 11.2

New Features

- ISE 11.2 software support.

- Virtex-6 and Spartan-6 support.

- Resource requirements reduced by up to 20%.

- New interface structure that provided more functionality for data flow control. (Not directly compatible with v1.0)

- Added support for 7-bit soft input.

- Added 1 DU (Decoder Unit) capability for lower throughput requirements.

- Added extrinsic input and output capability.

- Higher average throughputs due to increased scheduling efficiency.

- Added parallel data input and output capability.

Bug Fixes

- N/A

Known Issues

None

LogiCORE 3GPP LTE Turbo Decoder v1.0

Initial Release in ISE 10.1 IP Update 1

New Features

- Drop-in module for Spartan-3, Virtex-4, and Virtex-5 FPGAs

- Implements the 3GPP LTE specification

- Core contains the full interleaver

- Full 3GPP LTE block size range supported (i.e., 188 different block sizes in the range 40 - 6144)

- Dynamically selectable number of Iterations

- Number representation: two's complement fractional numbers

- Support for multiple processing units to provide increased throughput

Bug Fixes

- N/A

Known Issues

- Why doesn't the VHDL/Verilog Structural simulation work? See (Xilinx Answer 31302).

- Why is there a difference between the C Model simulation and the core output for maximum input values to the decoder? See (Xilinx Answer 31858).

Linked Answer Records

Child Answer Records

AR# 30630
Date Created 04/15/2008
Last Updated 12/15/2012
Status Active
Type General Article